公开(公告)号：US20220367263A1

公开(公告)日：2022-11-17

申请号：US17869462

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsueh Wen Tsau ,  Chia-Ching Lee ,  Cheng-Lung Hung ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

公开(公告)号：US20220216201A1

公开(公告)日：2022-07-07

申请号：US17656295

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Shih-Hang Chiu ,  Chih-Chang Hung ,  I-Wei Yang ,  Shu-Yuan Ku ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/11 ,  H01L29/06

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

公开(公告)号：US11302793B2

公开(公告)日：2022-04-12

申请号：US16943110

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/49

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

公开(公告)号：US20210399102A1

公开(公告)日：2021-12-23

申请号：US16909260

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.

公开(公告)号：US11164868B2

公开(公告)日：2021-11-02

申请号：US16777831

申请日：2020-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi-On Chui

IPC: H01L27/088

Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first gate structure of the first transistor may include a first high-k layer, a first capping layer and a first work function layer sequentially disposed on the substrate. A material of the first work function layer includes Ta. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer, a second capping layer and a second work function layer sequentially disposed on the substrate. The first capping layer and the second capping layer are formed of the same layer, and a material of the second work function layer is different from the material of the first work function layer.

公开(公告)号：US20210134799A1

公开(公告)日：2021-05-06

申请号：US17120921

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L27/092 ,  H01L21/324 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/321 ,  H01L21/027

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

公开(公告)号：US20210091077A1

公开(公告)日：2021-03-25

申请号：US16777831

申请日：2020-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi-On Chui

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8234

Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first gate structure of the first transistor may include a first high-k layer, a first capping layer and a first work function layer sequentially disposed on the substrate, wherein a material of the first work function layer includes Ta. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer, a second capping layer and a second work function layer sequentially disposed on the substrate, wherein the first capping layer and the second capping layer are formed of the same layer, and a material of the second work function layer is different from the material of the first work function layer.

公开(公告)号：US12218200B2

公开(公告)日：2025-02-04

申请号：US18359695

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092

Abstract: An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.

公开(公告)号：US12183638B2

公开(公告)日：2024-12-31

申请号：US18499650

申请日：2023-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Han Tsai ,  Chung-Chiang Wu ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

公开(公告)号：US20240363424A1

公开(公告)日：2024-10-31

申请号：US18769858

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsin-Han Tsai ,  Wei-Chin Lee ,  Chia-Ching Lee ,  Hung-Chin Chung ,  Cheng-Lung Hung ,  Da-Yuan Lee

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/42372

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.