公开(公告)号：US11127680B2

公开(公告)日：2021-09-21

申请号：US15632184

申请日：2017-06-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Kang Fu ,  Hsien-Chang Wu ,  Li-Lin Su ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528

摘要： In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

公开(公告)号：US20210057273A1

公开(公告)日：2021-02-25

申请号：US16547763

申请日：2019-08-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Ping Chen ,  Ming-Han Lee ,  Shin-Yi Yang ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Shau-Lin Shue ,  Min Cao

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US09728503B2

公开(公告)日：2017-08-08

申请号：US14926469

申请日：2015-10-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Hsien Peng ,  Chi-Liang Kuo ,  Ming-Han Lee ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/53238 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

公开(公告)号：US09324608B2

公开(公告)日：2016-04-26

申请号：US14720264

申请日：2015-05-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ching-Fu Yeh ,  Tz-Jun Kuo ,  Hsiang-Huan Lee ,  Ming-Han Lee

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/288

CPC分类号： H01L21/76873 ,  C25D3/38 ,  C25D7/123 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/44 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879

摘要： Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

公开(公告)号：US20160049373A1

公开(公告)日：2016-02-18

申请号：US14926469

申请日：2015-10-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Hsien Peng ,  Chi-Liang Kuo ,  Ming-Han Lee ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

摘要翻译： 在一些实施例中，本公开涉及导电互连层。 导电互连层具有设置在基板上的电介质层。 具有在水平面上方的上部和水平面下方的下部的开口向下延伸穿过介电层。 第一导电层填充开口的下部。 上阻挡层设置在覆盖开口上部的底部和侧壁表面的第一导电层上。 第二导电层设置在填充开口的上部的上阻挡层上。

公开(公告)号：US12080593B2

公开(公告)日：2024-09-03

申请号：US17859981

申请日：2022-07-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Ping Chen ,  Ming-Han Lee ,  Shin-Yi Yang ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Shau-Lin Shue ,  Min Cao

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76846 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266 ,  H01L21/3212

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US20240290653A1

公开(公告)日：2024-08-29

申请号：US18655495

申请日：2024-05-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chin-Lung Chung ,  Shin-Yi Yang ,  Ming-Han Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76834 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5329

摘要： A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.

公开(公告)号：US11929326B2

公开(公告)日：2024-03-12

申请号：US17556134

申请日：2021-12-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/324 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53238 ,  H01L21/324 ,  H01L21/76876 ,  H01L23/5226

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

公开(公告)号：US11742239B2

公开(公告)日：2023-08-29

申请号：US17501523

申请日：2021-10-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/535 ,  H01L23/532

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252

摘要： A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

公开(公告)号：US20230230877A1

公开(公告)日：2023-07-20

申请号：US18183004

申请日：2023-03-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chin-Lung Chung ,  Shin-Yi Yang ,  Ming-Han Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L21/76877 ,  H01L21/76832 ,  H01L21/7682 ,  H01L21/76819

摘要： A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.