- 专利标题: Via pre-fill on back-end-of-the-line interconnect layer
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申请号: US14926469申请日: 2015-10-29
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公开(公告)号: US09728503B2公开(公告)日: 2017-08-08
- 发明人: Chao-Hsien Peng , Chi-Liang Kuo , Ming-Han Lee , Hsiang-Huan Lee , Shau-Lin Shue
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Eschweiler & Potashnik, LLC
- 主分类号: H01L21/00
- IPC分类号: H01L21/00 ; H01L23/00 ; H01L23/532 ; H01L23/522 ; H01L21/768 ; H01L23/528
摘要:
In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.
公开/授权文献
- US20160049373A1 VIA PRE-FILL ON BACK-END-OF-THE-LINE INTERCONNECT LAYER 公开/授权日:2016-02-18
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