公开(公告)号：US08860119B2

公开(公告)日：2014-10-14

申请号：US13604073

申请日：2012-09-05

Applicant: Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

Inventor： Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L27/11582

Abstract: A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.

Abstract translation: 非易失性存储器件包括：衬底，其包括表面，形成在所述衬底的表面上的从所述表面垂直突出的沟道层，以及沿所述沟道层交替堆叠的多个层间电介质层和多个栅极电极层， 其中所述多个栅极电极层从所述多个层间电介质层突出。

公开(公告)号：US20130264629A1

公开(公告)日：2013-10-10

申请号：US13605213

申请日：2012-09-06

Applicant: Sung-Jin Whang ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Min-Soo Kim

Inventor： Sung-Jin Whang ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Min-Soo Kim

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7889

Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.

公开(公告)号：US20080079048A1

公开(公告)日：2008-04-03

申请号：US11862453

申请日：2007-09-27

Applicant: Yong-Soo Kim ,  Hong-Seon Yang ,  Se-Aug Jang ,  Seung-Ho Pyi ,  Kwon Hong ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Min-Gyu Sung ,  Seung-Ryong Lee ,  Tae-Yoon Kim

Inventor： Yong-Soo Kim ,  Hong-Seon Yang ,  Se-Aug Jang ,  Seung-Ho Pyi ,  Kwon Hong ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Min-Gyu Sung ,  Seung-Ryong Lee ,  Tae-Yoon Kim

IPC: H01L27/108 ,  H01L21/3205

CPC classification number: H01L29/66553 ,  H01L27/10876 ,  H01L29/518 ,  H01L29/66621

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

Abstract translation: 一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。 栅极导电层填充灯泡型凹陷区域。 栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

公开(公告)号：US08022501B2

公开(公告)日：2011-09-20

申请号：US12504427

申请日：2009-07-16

Applicant: Seung-Ho Pyi

Inventor： Seung-Ho Pyi

IPC: H01L21/768 ,  H01L21/70 ,  H01L23/522

CPC classification number: H01L21/76232 ,  H01L21/764 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

Abstract translation: 本发明涉及半导体器件及其分离方法。 半导体器件包括：硅衬底，其设置有在沟槽的底部具有至少一个硅柱的沟槽，其中硅柱变成微沟槽的侧壁; 以及选择性地和部分地填充到多个微沟槽中的器件隔离层。

公开(公告)号：US07968912B2

公开(公告)日：2011-06-28

申请号：US12749176

申请日：2010-03-29

Applicant: Yong-Soo Kim ,  Hong-Seon Yang ,  Seung-Ho Pyi ,  Tae-Hang Ahn

Inventor： Yong-Soo Kim ,  Hong-Seon Yang ,  Seung-Ho Pyi ,  Tae-Hang Ahn

IPC: H01L29/78 ,  H01L27/12

CPC classification number: H01L29/0847 ,  H01L21/18 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a gate formed over the substrate, a gate spacer provided against first and second sidewalls of the gate, and a source/drain region formed in the substrate proximate to the gate spacer. The source/drain region includes first and second epitaxial layers including Ge, wherein the second epitaxial layer which is formed over an interfacial layer between the first epitaxial layer and the substrate has a higher germanium concentration than that of the first epitaxial layer.

Abstract translation: 半导体器件包括衬底，形成在衬底上的栅极，设置在栅极的第一和第二侧壁上的栅极间隔，以及形成在靠近栅极间隔物的衬底中的源/漏区。 源极/漏极区包括包括Ge的第一和第二外延层，其中在第一外延层和衬底之间的界面层上形成的第二外延层具有比第一外延层更高的锗浓度。

公开(公告)号：US07579255B2

公开(公告)日：2009-08-25

申请号：US10879757

申请日：2004-06-30

Applicant: Seung-Ho Pyi

Inventor： Seung-Ho Pyi

IPC: H01L21/76

CPC classification number: H01L21/76232 ,  H01L21/764 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

Abstract translation: 本发明涉及半导体器件及其分离方法。 半导体器件包括：硅衬底，其设置有在沟槽的底部具有至少一个硅柱的沟槽，其中硅柱变成微沟槽的侧壁; 以及选择性地和部分地填充到多个微沟槽中的器件隔离层。

公开(公告)号：US07214584B2

公开(公告)日：2007-05-08

申请号：US11149297

申请日：2005-06-10

Applicant: Seung-Ho Pyi

Inventor： Seung-Ho Pyi

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/10814 ,  H01L27/10855

Abstract: Disclosed is a method for preventing a bunker defect generation on a lower portion of a cylinder type metal bottom electrode. The method includes the steps of: forming an etch stop layer on a bottom structure with a conductive region and an insulation region; forming a capacitor insulation layer on the etch stop layer; forming an opening exposing the conductive region by selectively etching the capacitor insulation layer and the etch stop layer; growing a selective epitaxial growth (SEG) layer in the conductive region exposed through the opening; forming a metal layer for a capacitor bottom electrode along a profile provided with the opening; forming an isolated capacitor bottom electrode by removing the metal layer until the capacitor insulation layer is exposed; and removing the capacitor insulation layer, thereby making the capacitor bottom electrode have a cylinder type structure.

Abstract translation: 公开了一种用于防止在气缸型金属底部电极的下部产生掩体缺陷的方法。 该方法包括以下步骤：在具有导电区域和绝缘区域的底部结构上形成蚀刻停止层; 在所述蚀刻停止层上形成电容器绝缘层; 通过选择性地蚀刻电容器绝缘层和蚀刻停止层，形成露出导电区域的开口; 在通过开口暴露的导电区域中生长选择性外延生长（SEG）层; 沿着设置有所述开口的轮廓形成用于电容器底部电极的金属层; 通过去除金属层形成隔离电容器底部电极，直到电容器绝缘层暴露; 并且去除电容器绝缘层，从而使电容器底部电极具有圆筒型结构。

公开(公告)号：US20050139951A1

公开(公告)日：2005-06-30

申请号：US10879757

申请日：2004-06-30

Applicant: Seung-Ho Pyi

Inventor： Seung-Ho Pyi

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L29/00

CPC classification number: H01L21/76232 ,  H01L21/764 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

Abstract translation: 本发明涉及半导体器件及其分离方法。 半导体器件包括：硅衬底，其设置有在沟槽的底部具有至少一个硅柱的沟槽，其中硅柱变成微沟槽的侧壁; 以及选择性地和部分地填充到多个微沟槽中的器件隔离层。