公开(公告)号：US09984925B2

公开(公告)日：2018-05-29

申请号：US15182024

申请日：2016-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Ho Jeon ,  Sang-Su Kim ,  Cheol Kim ,  Yong-Suk Tak ,  Myung-Geun Song ,  Gi-Gwan Park

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.

公开(公告)号：US09825153B2

公开(公告)日：2017-11-21

申请号：US15422907

申请日：2017-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Sunghyun Choi ,  Yong-Suk Tak ,  Bonyoung Koo ,  Jaejong Han

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/223 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

公开(公告)号：US09553141B2

公开(公告)日：2017-01-24

申请号：US14858069

申请日：2015-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jeong Yang ,  Soon-Wook Jung ,  Bong-Jin Kuh ,  Wan-Don Kim ,  Byung-Hong Chung ,  Yong-Suk Tak

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91

Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.

Abstract translation: 半导体器件包括多个下电极，其垂直长度大于衬底上的水平宽度，设置在下电极之间的支撑体，设置在下电极上的上电极，以及设置在下电极和下电极之间的电容器电介质层 上电极。 支撑体包括第一元件，第二元件和氧，第二元件的氧化物具有比第一元件的氧化物更高的带隙能量，并且支撑件中的第二元件的含量为约10原子％ 至90原子％。

公开(公告)号：US20240414925A1

公开(公告)日：2024-12-12

申请号：US18436574

申请日：2024-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)

Inventor： Seunghee Lee ,  Jin-Seong Park ,  Jihyun Kho ,  Dong-Gyu Kim ,  Yurim Kim ,  Yong-Suk Tak

IPC: H10B53/20 ,  H01L21/28 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: A semiconductor device has, in a gate insulating layer, in an XPS spectrum of O 1s obtained by an X-ray photoelectron spectroscopy (XPS) using a monochromatic aluminum Kα (1486.6 eV) source, a ratio (%) of an Al—O peak observed in a binding energy of about 530.3 eV to about 531.6 eV to all peaks of greater than or equal to about 80%.

公开(公告)号：US10026736B2

公开(公告)日：2018-07-17

申请号：US15384834

申请日：2016-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hyun Choi ,  Yong-Suk Tak ,  Gi-Gwan Park ,  Bon-Young Koo ,  Ki-Yeon Park ,  Won-Oh Seo

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/26 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.

公开(公告)号：US09991257B2

公开(公告)日：2018-06-05

申请号：US15013969

申请日：2016-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miseon Park ,  Jongryeol Yoo ,  Hyunjung Lee ,  Yong-Suk Tak ,  Bonyoung Koo ,  Sunjung Kim

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791

Abstract: A semiconductor device may include fin active regions extending parallel to each other on a substrate, an isolation region between the fin active regions, gate patterns intersecting the fin active regions and extending parallel to each other, source/drain areas on the fin active regions between the gate patterns and fin active region spacers contacting side surfaces of the fin active regions and formed over a surface of the isolation region between the fin active regions. Uppermost levels of the fin active region spacers may be higher than interfaces between the fin active regions and the source/drain areas. The upper surface of the isolation region may be lower than bottom surfaces of the source/drain areas.

公开(公告)号：US09142558B2

公开(公告)日：2015-09-22

申请号：US14066000

申请日：2013-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jeong Yang ,  Soon-Wook Jung ,  Bong-Jin Kuh ,  Wan-Don Kim ,  Byung-Hong Chung ,  Yong-Suk Tak

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91

Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.

Abstract translation: 半导体器件包括多个下电极，其垂直长度大于衬底上的水平宽度，设置在下电极之间的支撑体，设置在下电极上的上电极，以及设置在下电极和下电极之间的电容器电介质层 上电极。 支撑体包括第一元件，第二元件和氧，第二元件的氧化物具有比第一元件的氧化物更高的带隙能量，并且支撑件中的第二元件的含量为约10原子％ 至90原子％。