知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.019 seconds)

    SYSTEMS AND METHODS FOR WRITE AND FLUSH SUPPORT IN HYBRID MEMORY
    13.
    发明申请
    SYSTEMS AND METHODS FOR WRITE AND FLUSH SUPPORT IN HYBRID MEMORY 审中-公开

    公开(公告)号：US20180329651A1

    公开(公告)日：2018-11-15

    申请号：US15669851

    申请日：2017-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Heehyun Nam ,  Youngjin Cho ,  Sun-Young Lim

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0685

    Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

    Memory system
    15.
    发明授权
    Memory system 有权
    内存系统

    公开(公告)号：US09454496B2

    公开(公告)日：2016-09-27

    申请号：US14185143

    申请日：2014-02-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sun-Young Lim

    IPC: G06F13/12 ,  G06F13/38 ,  G06F12/14 ,  G06F12/10

    CPC classification number: G06F12/145 ,  G06F12/1027 ,  G06F2212/651

    Abstract: A memory system is provided, which includes a real memory space and a virtual memory space. The memory system includes a memory device having a first memory space which is accessed using a first memory address and a second memory space which is accessed using a second memory address, and a memory controller configured to control access to the memory device; wherein the memory controller is configured to translate the first memory address into the second memory address mapped thereto in response to a request for access to the first memory space, access the second memory space using the translated second memory address, and access the second memory space using the non-translated second memory address, in response to a request for access to the second memory space.

    Abstract translation: 提供了一种存储器系统，其包括实际存储器空间和虚拟存储器空间。 存储器系统包括具有使用第一存储器地址访问的第一存储器空间和使用第二存储器地址访问的第二存储器空间的存储器件，以及被配置为控制对存储器件的访问的存储器控​​制器; 其中所述存储器控制器被配置为响应于访问所述第一存储器空间的请求将所述第一存储器地址转换为映射到其的所述第二存储器地址，使用所转换的第二存储器地址访问所述第二存储器空间，以及访问所述第二存储器空间 响应于访问第二存储器空间的请求，使用非翻译的第二存储器地址。

    Page replacement method and memory system using the same
    16.
    发明授权
    Page replacement method and memory system using the same 有权
    页面替换方法和使用相同的内存系统

    公开(公告)号：US09195579B2

    公开(公告)日：2015-11-24

    申请号：US13754161

    申请日：2013-01-30

    Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation, Sungkyunkwan University

    Inventor： Oh-Seong Kwon ,  Hwansoo Han ,  Sun-Young Lim ,  Seonggun Kim

    IPC: G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/121 ,  G06F2212/205 ,  G06F2212/222

    Abstract: A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.

    Abstract translation: 存储器系统包括中央处理单元（CPU），电耦合到CPU的非易失性存储器和主存储器，其被配置为响应于由所述主存储器发出的第一命令来交换其中的目标代码页的输入代码页 中央处理器。 主存储器可被配置为在主存储器的页面容量处于阈值容量的情况下将主存储器中的目标代码页交换到非易失性存储器。 CPU还可以被配置为在目标代码页上执行使用分析频率，以确定目标代码页是否被交换到非易失性存储器或被丢弃。 输入代码页可以由磁盘驱动器存储设备提供，并且主存储器可以是易失性存储器。

    MEMORY SYSTEM CAPABLE OF RE-MAPPING ADDRESS
    17.
    发明申请
    MEMORY SYSTEM CAPABLE OF RE-MAPPING ADDRESS 审中-公开
    可重新映射地址的记忆系统

    公开(公告)号：US20150199230A1

    公开(公告)日：2015-07-16

    申请号：US14524476

    申请日：2014-10-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MI-KYOUNG PARK ,  Dong-Yang Lee ,  Sun-Young Lim ,  Bu-Il Jung ,  Ju-Yun Jung ,  Sung-Ho Cho ,  Hee-Joo Choi ,  Min-Yeab Choo ,  Hyuk Han

    IPC: G06F11/10

    CPC classification number: G11C29/76 ,  G11C8/06 ,  G11C2029/4402

    Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.

    Abstract translation: 存储器系统包括存储器控制器，存储单元阵列，位置信息存储单元，地址映射表，地址转换单元和映射信息计算单元。 存储器控制器产生逻辑地址信号和地址重映射命令。 存储单元阵列包括多个逻辑块。 位置信息存储单元存储与包含在存储单元阵列中的故障存储单元对应的位置信息。 地址映射表存储地址映射信息。 地址转换单元基于地址映射信息将逻辑地址信号转换为对应于存储单元阵列的物理地址信号。 映射信息计算单元根据映射信息计算单元接收地址重映射命令，根据位置信息生成地址映射信息，以减少包括故障存储单元的逻辑块的数量。

    Memory module and memory system relating thereto
    19.
    发明授权
    Memory module and memory system relating thereto 有权

    公开(公告)号：US11481149B2

    公开(公告)日：2022-10-25

    申请号：US16706078

    申请日：2019-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sun-Young Lim ,  Ki-Seok Oh ,  Sungyong Seo ,  Youngjin Cho ,  Insu Choi

    IPC: G06F3/06 ,  G11C14/00 ,  G11C11/406

    Abstract: A memory module including at least one memory and a memory control circuit to control the at least one memory and to generate an internal operation request including an information regarding internal operation time when the memory module need the internal operation time. The memory control circuit is to transfer the internal operation request to an external device, to receive a first command from the external device in response to the internal operation request and including an information of whether the internal operation time is approved, and to perform the internal operation during the internal operation time based on the first command.

Patent Agency Ranking