公开(公告)号：US10756179B2

公开(公告)日：2020-08-25

申请号：US16423641

申请日：2019-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/165 ,  H01L29/10 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US20190393315A1

公开(公告)日：2019-12-26

申请号：US16205851

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo NOH ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/06

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US10204983B2

公开(公告)日：2019-02-12

申请号：US15444550

申请日：2017-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Dae Suk ,  Seung Min Song ,  Geum Jong Bae

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate. The spacer connector may connect the first gate spacer and the second gate spacer to each other.

公开(公告)号：US10128379B2

公开(公告)日：2018-11-13

申请号：US15647903

申请日：2017-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min Song ,  Woo Seok Park ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.

公开(公告)号：US20240290834A1

公开(公告)日：2024-08-29

申请号：US18214221

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehong LEE ,  Seung Min Song ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L27/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L29/861

CPC classification number: H01L29/0653 ,  H01L27/0629 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/8611

Abstract: Provided is a semiconductor device including: a 1st source/drain region and a 1st backside contact structure, vertically below the 1st source/drain region, connected to the 1st source/drain region; a 2nd source/drain region and a 1st placeholder isolation structure vertically below the 2nd source/drain region; and a backside isolation structure, on a back side of the semiconductor device, surrounding the 1st backside contact structure and the 1st placeholder isolation structure.

公开(公告)号：US11967614B2

公开(公告)日：2024-04-23

申请号：US17715273

申请日：2022-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L29/08 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L29/045 ,  H01L29/78696

Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.

公开(公告)号：US20240096889A1

公开(公告)日：2024-03-21

申请号：US18173847

申请日：2023-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Min Song ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Integrated circuit devices may include a first upper channel region on a substrate, a first lower channel region between the substrate and the first upper channel region, a first intergate insulator that is between the first lower channel region and the first upper channel region and includes a lower portion and an upper portion, an upper gate electrode, and a lower gate electrode between the substrate and the upper gate electrode. The first upper channel region and the upper portion of the first intergate insulator may be in the upper gate electrode. The first lower channel region and the lower portion of the first intergate insulator are in the lower gate electrode.

公开(公告)号：US11322589B2

公开(公告)日：2022-05-03

申请号：US16752418

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/04 ,  H01L29/786

Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.

公开(公告)号：US11908952B2

公开(公告)日：2024-02-20

申请号：US17840737

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Woo Seok Park ,  Dong Chan Suh ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78618

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

公开(公告)号：US11594550B2

公开(公告)日：2023-02-28

申请号：US16852907

申请日：2020-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Min Kim ,  Seung Min Song ,  Jae Hoon Shin ,  Joong Shik Shin ,  Geun Won Lim

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L21/311 ,  H01L27/11565

Abstract: A nonvolatile memory device with improved product reliability and a method of fabricating the same is provided. The nonvolatile memory device comprises a substrate, a first mold structure disposed on the substrate and including a plurality of first gate electrodes, a second mold structure disposed on the first mold structure and including a plurality of second gate electrodes and a plurality of channel structures intersecting the first gate electrodes and the second gate electrodes by penetrating the first and second mold structures, wherein the first mold structure includes first and second stacks, which are spaced apart from each other, and the second mold structure includes a third stack, which is stacked on the first stack, a fourth stack, which is stacked on the second stack, and first connecting parts, which connect the third and fourth stacks.