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    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    12.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20230289072A1

    公开(公告)日：2023-09-14

    申请号：US18045590

    申请日：2022-10-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun Cho ,  Youngju Kim ,  Younghwa Kim ,  Yujung Song ,  Reum Oh

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0629 ,  G06F3/064

    Abstract: A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.

    Semiconductor memory device and system including the same
    13.
    发明授权
    Semiconductor memory device and system including the same 有权

    公开(公告)号：US11599301B2

    公开(公告)日：2023-03-07

    申请号：US17245325

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Haesuk Lee ,  Reum Oh ,  Youngcheon Kwon ,  Beomyong Kil ,  Jemin Ryu ,  Jihyun Choi

    IPC: G06F3/06 ,  G11C7/22

    Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

    High bandwidth memory device and system device having the same
    15.
    发明授权
    High bandwidth memory device and system device having the same 有权

    公开(公告)号：US11194505B2

    公开(公告)日：2021-12-07

    申请号：US17173754

    申请日：2021-02-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

    IPC: G11C5/02 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

    Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.

    WAFER LEVEL METHODS OF TESTING SEMICONDUCTOR DEVICES USING INTERNALLY-GENERATED TEST ENABLE SIGNALS
    16.
    发明申请
    WAFER LEVEL METHODS OF TESTING SEMICONDUCTOR DEVICES USING INTERNALLY-GENERATED TEST ENABLE SIGNALS 审中-公开

    公开(公告)号：US20200371157A1

    公开(公告)日：2020-11-26

    申请号：US16665318

    申请日：2019-10-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ahn Choi ,  Reum Oh

    IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185

    Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

    Memory device sampling data using control signal transmitted through TSV
    17.
    发明授权
    Memory device sampling data using control signal transmitted through TSV 有权

    公开(公告)号：US10740033B2

    公开(公告)日：2020-08-11

    申请号：US16197877

    申请日：2018-11-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： So-young Kim ,  Reum Oh ,  Haesuk Lee

    IPC: G06F3/06 ,  H01L25/18 ,  G11C11/4093 ,  G11C11/4076 ,  H01L23/48 ,  H01L25/065 ,  G11C11/408

    Abstract: A memory die of a memory device includes a first first-in first-out (FIFO) circuit that samples data output from a memory cell array and outputs the data to a buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. A buffer die of the memory device includes a second FIFO circuit that samples the data output from the first FIFO unit based on the control signal transmitted from the memory die through a second through silicon via, a calibration circuit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.

    Memory device for performing internal process and operating method thereof
    18.
    发明授权
    Memory device for performing internal process and operating method thereof 有权

    公开(公告)号：US10410685B2

    公开(公告)日：2019-09-10

    申请号：US16293372

    申请日：2019-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Reum Oh ,  Je-Min Ryu ,  Pavan Kumar Kasibhatla

    IPC: G11C5/02 ,  G06F12/0893 ,  G11C29/12 ,  G11C29/48 ,  G11C7/10 ,  G06F12/084 ,  H01L25/18

    Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

    Stacked semiconductor device and system including the same
    19.
    发明授权
    Stacked semiconductor device and system including the same 有权

    公开(公告)号：US10373661B2

    公开(公告)日：2019-08-06

    申请号：US15479971

    申请日：2017-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hae-Suk Lee ,  Reum Oh ,  Jin-Seong Park ,  Seung-Han Woo

    IPC: G11C5/02 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10 ,  H04L7/033 ,  H03K19/21 ,  G11C7/22 ,  G11C7/12 ,  H03K3/356 ,  H01L25/065

    Abstract: A stacked semiconductor device includes a plurality of semiconductor dies stacked in a vertical direction, first and second signal paths, a transmission unit and a reception unit. The first and second signal paths electrically connect the plurality of semiconductor dies, where each of the first signal path and the second signal path includes at least one through-substrate via. The transmission unit generates a first driving signal and a second driving signal in synchronization with transitioning timing of a transmission signal to output the first driving signal to the first signal path and output the second driving signal to the second signal path. The reception unit receives a first attenuated signal corresponding to the first driving signal from the first signal path and receives a second attenuated signal corresponding to the second driving signal from the second signal path to generate a reception signal corresponding to the transmission signal.

    Stacked memory device and a memory chip including the same
    20.
    发明授权
    Stacked memory device and a memory chip including the same 有权

    公开(公告)号：US10331354B2

    公开(公告)日：2019-06-25

    申请号：US15617450

    申请日：2017-06-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hak-Soo Yu ,  Je-Min Ryu ,  Reum Oh ,  Pavan Kumar Kasibhatla ,  Seok-In Hong

    IPC: G06F3/06 ,  G11C5/02 ,  G11C5/06 ,  G11C5/04

    Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

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