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    Memory device transmitting and receiving data at high speed and low power
    6.
    发明授权
    Memory device transmitting and receiving data at high speed and low power 有权

    公开(公告)号：US11295808B2

    公开(公告)日：2022-04-05

    申请号：US17084345

    申请日：2020-10-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byongmo Moon ,  Jihye Kim ,  Je Min Ryu ,  Beomyong Kil ,  Sungoh Ahn

    IPC: G11C11/4076 ,  G11C11/4093 ,  G06F3/06 ,  G11C11/4096 ,  H01L25/18

    Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

    MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER
    8.
    发明申请
    MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER 有权

    公开(公告)号：US20210225426A1

    公开(公告)日：2021-07-22

    申请号：US17084345

    申请日：2020-10-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byongmo MOON ,  Jihye Kim ,  Je Min Ryu ,  Beomyong Kil ,  Sungoh Ahn

    IPC: G11C11/4093 ,  H01L25/18 ,  G11C11/4076 ,  G11C11/4096 ,  G06F3/06

    Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

    Semiconductor memory device and method of operating a semiconductor device in a processor mode or a normal mode
    9.
    发明授权
    Semiconductor memory device and method of operating a semiconductor device in a processor mode or a normal mode 有权

    公开(公告)号：US10592467B2

    公开(公告)日：2020-03-17

    申请号：US15493292

    申请日：2017-04-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Je Min Ryu ,  Reum Oh ,  Hak-Soo Yu

    IPC: G06F3/06 ,  G06F15/78

    Abstract: An operation method of a semiconductor memory device including a memory cell array and an internal processor configured to perform an internal processing operation includes receiving at the memory device a first mode indicator that indicates whether the memory device should operate in a processor mode or in a normal mode, receiving at the memory device processing information for the memory device, when the first mode indicator indicates that the memory device should operate in the processor mode, storing the processing information in a first memory cell region of the memory cell array, using the stored processing information to perform internal processing by the internal processor, and storing a result of the internal processing in the memory cell array.

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