公开(公告)号：US20190279963A1

公开(公告)日：2019-09-12

申请号：US16125975

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeungHan WOO ,  Je Min Ryu ,  Reum Oh ,  Moonhee Oh ,  BumSuk Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  G01R31/28

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

公开(公告)号：US20210104498A1

公开(公告)日：2021-04-08

申请号：US17124762

申请日：2020-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeungHan WOO ,  Je Min RYU ,  Reum OH ,  Moonhee OH ,  BumSuk LEE

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  G01R31/28

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

公开(公告)号：US20190237390A1

公开(公告)日：2019-08-01

申请号：US16263408

申请日：2019-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung RHO ,  Chisung OH ,  Kyomin SOHN ,  Yong-Ki KIM ,  Jong-Ho MOON ,  SeungHan WOO ,  Jaeyoun YOUN

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

Abstract: A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.