-
公开(公告)号：US11228901B2
公开(公告)日：2022-01-18
申请号：US16833115
申请日：2020-03-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daesoo Park , Jinwoo Lee , Yongbeom Kwon
Abstract: Various embodiments relate to a method and an electronic device for installing a subscriber profile. The method includes obtaining network operator-related information. The method also includes identifying whether download of an embedded subscriber identity module (eSIM) profile is allowed based on the network operator-related information. The method further includes downloading the eSIM profile when download of the eSIM profile is allowed.
-
公开(公告)号：US20200335361A1
公开(公告)日：2020-10-22
申请号：US16692051
申请日：2019-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hun Jae JANG , Seung Min Shin , Seok Hoon Kim , In Gi Kim , Tae-Hong Kim , Kun Tack Lee , Jinwoo Lee , Ji Hoon Cha , Yong Jun Choi
Abstract: A wafer cleaning equipment includes a housing to be positioned adjacent to a wafer, a hollow region in the housing, a laser module that outputs a laser beam having a profile of the laser beam includes a first region having a first intensity and a second region having a second intensity greater than the first intensity, the laser beam being output into the hollow region, and a transparent window that covers an upper part of the hollow region and transmits the laser beam to be incident on an entirety of a lower surface of the wafer.
-
公开(公告)号：US09985204B2
公开(公告)日：2018-05-29
申请号：US15451961
申请日：2017-03-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinwoo Lee , Jeonghee Park , Dongho Ahn , Zhe Wu , Heeju Shin , Ja bin Lee
CPC classification number: H01L45/141 , H01L43/08 , H01L43/10 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/16
Abstract: A semiconductor memory device including first lines and second lines overlapping and intersecting each other, variable resistance memory elements disposed at intersections between the first lines and the second lines, and switching elements disposed between the variable resistance memory elements and the first lines. At least one of the switching elements includes first and second chalcogenide compound layers, and conductive nano-dots disposed between the first and second chalcogenide compound layers.
-
公开(公告)号：US20250120095A1
公开(公告)日：2025-04-10
申请号：US18802058
申请日：2024-08-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinwoo Lee , Geonhui Han , Hyunsang Hwang , Dongho Ahn , Jinmyung Choi
IPC: H10B63/00
Abstract: A semiconductor device includes a substrate, source/drain regions on the substrate, a channel layer between the source/drain regions and including indium gallium zinc oxide (IGZO), a variable resistance layer on the channel layer and including metal oxide that satisfies a stoichiometric ratio of metal to oxygen, a gate insulating layer on the variable resistance layer and including metal oxide that does not satisfy the stoichiometric ratio of metal to oxygen, and a gate electrode on the gate insulating layer.
-
公开(公告)号：US20250027875A1
公开(公告)日：2025-01-23
申请号：US18775796
申请日：2024-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinwoo Lee , Seungryeol Oh , Hidong Kwak , Jeongho Ahn , Seongsil Lee , Suyoung Lee , Hyeongcheol Lee
IPC: G01N21/31
Abstract: An optical imaging device includes a pulse generator including a pulse generating device configured to generate pulse lasers and a pulse expander configured to receive a pulse laser from the pulse generating device, and generate a broadened pulse laser by expanding a spectrum and width of the received pulse laser, an optical assembly including an objective lens configured to receive the broadened pulse laser and pass the received broadened pulse laser to a target object, and a light receiver including a light receiving device configured to receive a reflected pulse laser corresponding to the broadened pulse laser reflected from the target object and convert the reflected pulse laser into an electrical signal, and at least one processor configured to generate a spectral image set based on the electrical signal generated by the light receiving device.
-
Patent Agency Ranking
公开(公告)号：US20240365567A1
公开(公告)日：2024-10-31
申请号：US18471585
申请日：2023-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinwoo Lee , Dongho Ahn , Jin Myung Choi
IPC: H10B63/00
CPC classification number: H10B63/845 , H10B63/34
Abstract: A semiconductor device according to an embodiment includes a gate stack structure and a channel structure. The gate stack structure includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on a substrate in a first direction perpendicular to an upper surface of the substrate. The channel structure includes a portion penetrating through the gate stack structure and extending in the first direction. The channel structure includes a channel layer, a resistance change layer, and a metal-containing layer sequentially stacked. The metal-containing layer includes a metal or a metal compound.
-
公开(公告)号：US11968749B2
公开(公告)日：2024-04-23
申请号：US17646322
申请日：2021-12-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daesoo Park , Jinwoo Lee , Yongbeom Kwon
Abstract: Various embodiments relate to a method and an electronic device for installing a subscriber profile. The method includes obtaining network operator-related information. The method also includes identifying whether download of an embedded subscriber identity module (eSIM) profile is allowed based on the network operator-related information. The method further includes downloading the eSIM profile when download of the eSIM profile is allowed.
-
公开(公告)号：US11795550B2
公开(公告)日：2023-10-24
申请号：US17313534
申请日：2021-05-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungah Kim , Mihyun Park , Jinwoo Lee , Keonyoung Kim , Hyosan Lee , Hoon Han , Jin Uk Lee , Jung Hun Lim
IPC: C23F1/26 , C23F1/30 , H01L21/311 , H01L21/306 , B81C1/00 , C09K13/04
CPC classification number: C23F1/26 , B81C1/00539 , C09K13/04 , C23F1/30 , H01L21/30604 , H01L21/31111
Abstract: A method of etching a metal barrier layer and a metal layer is provided. The method includes forming the metal barrier layer and the metal layer on a substrate, and using an etching composition to etch the metal barrier layer and the metal layer. The etching composition may include an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methane sulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or a combination thereof, a metal etching inhibitor including a compound expressed by Chemical Formula 1, and a metal oxide solubilizer selected from phosphoric acid, phosphate, carboxylic acid having 3 to 20 carbon atoms, or a combination thereof.
-
公开(公告)号：US11616197B2
公开(公告)日：2023-03-28
申请号：US16988957
申请日：2020-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ja Bin Lee , Zhe Wu , Kwangmin Park , Gwangguk An , Dongho Ahn , Seung-Geun Yu , Jinwoo Lee
Abstract: A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.
-
公开(公告)号：US20180019281A1
公开(公告)日：2018-01-18
申请号：US15454064
申请日：2017-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ja bin LEE , Jeonghee Park , Dongho Ahn , Zhe Wu , Heeju Shin , Jinwoo Lee
CPC classification number: H01L27/2427 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1625
Abstract: A variable resistance memory device may include separate memory cells between separate vertical intersections of first conductive lines extending in a first direction and second conductive lines extending in a second direction intersecting the first direction. A memory cell may include a switching element and a variable resistance structure coupled in series between a first conductive line and a second conductive line. The switching element may include at least one insulative impurity and a chalcogenide material. The variable resistance structure may reversibly switch phases, between a crystalline state and an amorphous state, at a first phase transition temperature, and the switching element may reversibly switch phases, between a crystalline state and an amorphous state, at a second phase transition temperature, where the second phase transition temperature is greater than the first phase transition temperature.
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.021 seconds)
