公开(公告)号：US08790976B2

公开(公告)日：2014-07-29

申请号：US13942149

申请日：2013-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Oh ,  Sung-Lae Cho ,  Byoung-Jae Bae ,  Ik-Soo Kim ,  Dong-Hyun Im ,  Doo-Hwan Park ,  Kyoung-Ha Eom ,  Sung-Un Kwon ,  Chul-Ho Shin ,  Sang-Sup Jeong

IPC: H01L21/336

CPC classification number: H01L45/1683 ,  H01L27/2463 ,  H01L45/06

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract translation: 形成基板上的导电图案。 形成具有露出导电图案的开口的绝缘层。 底部电极形成在导电图案和开口的第一侧壁上。 在底部电极和开口的第二侧壁上形成间隔物。 间隔件和底部电极形成为低于绝缘层的顶表面。 数据存储插头形成在底部电极和间隔件上。 数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。 在数据存储插头上形成位线。

公开(公告)号：US10833088B2

公开(公告)日：2020-11-10

申请号：US16805585

申请日：2020-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyun Im ,  Daehyun Kim ,  Hoon Park ,  Jae-Hong Seo ,  Chunhyung Chung ,  Jae-Joong Choi

IPC: H01L29/49 ,  H01L27/108 ,  H01L21/283 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

公开(公告)号：US20170345824A1

公开(公告)日：2017-11-30

申请号：US15603668

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon MA ,  Jun-Noh Lee ,  Dong-Hyun Im ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US09543196B2

公开(公告)日：2017-01-10

申请号：US14674332

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Park ,  Dong-Hyun Im ,  Soon-Gun Lee ,  Jong-Myeong Lee ,  Han-Jin Lim

IPC: H01L21/20 ,  H01L21/82 ,  H01L21/768 ,  B82Y10/00 ,  H01L21/02 ,  H01L27/108 ,  H01L49/02 ,  H01L29/41

CPC classification number: H01L21/76837 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/91 ,  H01L29/413 ,  H01L2221/1094

Abstract: Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

Abstract translation: 制造半导体器件的方法可以包括形成引导图案，其暴露基底图案，通过执行第一纳米线生长工艺在基底图案上形成第一纳米线，在第一纳米线之间形成第一模制绝缘层， 去除纳米线，并在孔中形成包括导电材料的第一电极。

公开(公告)号：US20160035676A1

公开(公告)日：2016-02-04

申请号：US14681313

申请日：2015-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hyun Im ,  Hyun Park ,  Soongun Lee ,  Chang Seok Lee ,  Sangwon Kim ,  Seongjun Park ,  Hyeon Jin Shin ,  Hanjin Lim

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L29/06 ,  H01L27/108 ,  H01L21/02

CPC classification number: H01L23/53276 ,  H01L21/02527 ,  H01L21/32139 ,  H01L21/768 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices may include a substrate including an active region defined by a device isolation layer, source/drain regions in the active region, word lines extending in a first direction parallel to the active region and being arranged in a second direction crossing the first direction, a bit line pattern extending in the second direction and crossing over a portion of the active region positioned between the word lines, and a graphene pattern covering at least a portion of the bit line pattern.

Abstract translation: 半导体器件可以包括：衬底，其包括由器件隔离层限定的有源区，有源区中的源极/漏极区，在与有源区平行的第一方向上延伸的并且沿与第一方向交叉的第二方向布置的字线; 在第二方向上延伸并与位于字线之间的有源区的一部分交叉的位线图形，以及覆盖位线图案的至少一部分的石墨烯图案。