SEMICONDUCTOR DEVICES
    1.
    发明申请

    公开(公告)号:US20240389348A1

    公开(公告)日:2024-11-21

    申请号:US18417089

    申请日:2024-01-19

    Abstract: A semiconductor device includes a capacitor structure. The capacitor structure includes a lower electrode, a dielectric layer on the lower electrode, an upper electrode on the dielectric layer, and a defect preventing layer between the lower electrode and the upper electrode. The defect preventing layer includes at least one of a first defect preventing layer between the lower electrode and the dielectric layer or a second defect preventing layer between the upper electrode and the dielectric layer. The dielectric layer includes a ferroelectric layer that includes at least one of a ferroelectric material or an anti-ferroelectric material. The ferroelectric layer includes a polarization region and a non-polarization region surrounded by the polarization region.

    SEMICONDUCTOR DEVICE
    2.
    发明公开

    公开(公告)号:US20240008254A1

    公开(公告)日:2024-01-04

    申请号:US18116071

    申请日:2023-03-01

    CPC classification number: H10B12/315 H10B12/033

    Abstract: A semiconductor device includes a substrate, a lower electrode above the substrate, the lower electrode extending in a vertical direction, a support surrounding a side wall of the lower electrode and supporting the lower electrode, a dielectric layer on the lower electrode and the support, and an upper electrode on the dielectric layer, wherein the lower electrode includes a base electrode layer and an insertion layer, the base electrode layer containing a halogen element, and the insertion layer containing carbon, and the insertion layer is inserted in a portion of the lower electrode, the portion of the lower electrode being adjacent to the support and the dielectric layer.

    SEMICONDUCTOR DEVICE
    3.
    发明公开

    公开(公告)号:US20230253445A1

    公开(公告)日:2023-08-10

    申请号:US17993943

    申请日:2022-11-24

    CPC classification number: H01L28/75 H01L28/91 H10B12/315 H01L28/92 H10B12/0335

    Abstract: A semiconductor device includes: a substrate; a contact plug on the substrate; a lower electrode electrically connected to the contact plug, and including a first electrode layer, a first buffer layer, and a second electrode layer, sequentially stacked; a first support layer in contact with an upper surface of the lower electrode and disposed to overlap at least a portion of the lower electrode, the first support layer extending in a direction parallel to an upper surface of the substrate; a dielectric layer disposed on the lower electrode and the first support layer; and an upper electrode disposed on the dielectric layer. The lower electrode comprises a first region overlapping the first support layer, and having a first height; and a second region not overlapping the first support layer, and having a second height lower than the first height.

    SEMICONDUCTOR DEVICES
    5.
    发明公开

    公开(公告)号:US20240357832A1

    公开(公告)日:2024-10-24

    申请号:US18512331

    申请日:2023-11-17

    CPC classification number: H10B53/30 H10B53/40

    Abstract: A semiconductor device includes a bit line structures on a substrate, extending in a first direction, and being spaced apart from each other in a second direction; channels contacting upper surfaces of the bit line structures and being spaced apart from each other in the first and second directions; upper gate structures extending in the second direction and surrounding the channels disposed in the second direction, the upper gate structures being spaced apart in the first direction; and a capacitor structure including first capacitor electrodes respectively on the channels; a dielectric layer on the first capacitor electrodes, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode layer on the dielectric layer; and capacitor plate electrodes on the second capacitor electrode layer, the capacitor plate electrodes each extending in the second direction and being spaced apart from each other in the first direction.

    Semiconductor devices
    7.
    发明授权

    公开(公告)号:US12057470B2

    公开(公告)日:2024-08-06

    申请号:US17809727

    申请日:2022-06-29

    CPC classification number: H01L28/55 H01L28/65 H01L28/75 H10B12/482 H01L28/82

    Abstract: A semiconductor device includes a capacitor. The capacitor includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes a first dielectric layer and a second dielectric layer that are interposed between the bottom electrode and the top electrode and are stacked in the first direction. The first dielectric layer is anti-ferroelectric, and the second dielectric layer is ferroelectric. A thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.

    CAPACITOR AND DRAM DEVICE INCLUDING THE SAME

    公开(公告)号:US20230209804A1

    公开(公告)日:2023-06-29

    申请号:US17935148

    申请日:2022-09-26

    CPC classification number: H01L27/10814 H01L27/10823

    Abstract: A capacitor is described. The capacitor includes a lower electrode, a dielectric layer structure disposed on the lower electrode, and an upper electrode disposed on the dielectric layer structure. The dielectric layer structure includes a first dielectric layer, a second dielectric layer contacting the first dielectric layer, and a third dielectric layer contacting the second dielectric layer. Each of the first to third dielectric layers includes a material with a crystalline structure. The second dielectric layer includes an oxide having ferroelectric or antiferroelectric properties, and the second dielectric layer includes a material in which at least two different crystal phases are mixed.

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明公开

    公开(公告)号:US20240321943A1

    公开(公告)日:2024-09-26

    申请号:US18601032

    申请日:2024-03-11

    CPC classification number: H01L28/75 H01L28/65 H10B12/31 H10B12/482 H10B12/488

    Abstract: A semiconductor memory device includes an upper electrode, a lower electrode, an anti-ferroelectric layer disposed between the upper electrode and the lower electrode and including an anti-ferroelectric, an oxide layer disposed on a first surface of the anti-ferroelectric layer and including a high dielectric material, and a metal oxide layer disposed on a second surface of the anti-ferroelectric layer opposite to the first surface. A thickness of each of the oxide layer and the metal oxide layer is less than a thickness of the anti-ferroelectric layer.

Patent Agency Ranking