公开(公告)号：US08790976B2

公开(公告)日：2014-07-29

申请号：US13942149

申请日：2013-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Oh ,  Sung-Lae Cho ,  Byoung-Jae Bae ,  Ik-Soo Kim ,  Dong-Hyun Im ,  Doo-Hwan Park ,  Kyoung-Ha Eom ,  Sung-Un Kwon ,  Chul-Ho Shin ,  Sang-Sup Jeong

IPC: H01L21/336

CPC classification number: H01L45/1683 ,  H01L27/2463 ,  H01L45/06

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract translation: 形成基板上的导电图案。 形成具有露出导电图案的开口的绝缘层。 底部电极形成在导电图案和开口的第一侧壁上。 在底部电极和开口的第二侧壁上形成间隔物。 间隔件和底部电极形成为低于绝缘层的顶表面。 数据存储插头形成在底部电极和间隔件上。 数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。 在数据存储插头上形成位线。

公开(公告)号：US20130302966A1

公开(公告)日：2013-11-14

申请号：US13942149

申请日：2013-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Oh ,  Sung-Lae Cho ,  Byoung-Jae Bae ,  Ik-Soo Kim ,  Dong-Hyun Im ,  Doo-Hwan Park ,  Kyoung-Ha Eom ,  Sung-Un Kwon ,  Chul-Ho Shin ,  Sang-Sup Jeong

IPC: H01L45/00

CPC classification number: H01L45/1683 ,  H01L27/2463 ,  H01L45/06

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract translation: 形成基板上的导电图案。 形成具有露出导电图案的开口的绝缘层。 底部电极形成在导电图案和开口的第一侧壁上。 在底部电极和开口的第二侧壁上形成间隔物。 间隔件和底部电极形成为低于绝缘层的顶表面。 数据存储插头形成在底部电极和间隔件上。 数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。 在数据存储插头上形成位线。

公开(公告)号：US09837273B2

公开(公告)日：2017-12-05

申请号：US15223710

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Sub Lee ,  Kyoung-Ha Eom ,  Ha-Neul Lee ,  Sang-Gyo Chung

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/108

CPC classification number: H01L21/0337 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11582 ,  H01L28/00

Abstract: A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.

公开(公告)号：US20170103891A1

公开(公告)日：2017-04-13

申请号：US15223710

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Sub LEE ,  Kyoung-Ha Eom ,  Ha-Neul Lee ,  Sang-Gyo Chung

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11582 ,  H01L28/00

Abstract: A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.