公开(公告)号：US09929235B1

公开(公告)日：2018-03-27

申请号：US15463551

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US11961806B2

公开(公告)日：2024-04-16

申请号：US17352503

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Noh Yeong Park ,  Beomjin Park ,  Dong Il Bae ,  Sangwon Baek ,  Hyun-Seung Song

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/562 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.

公开(公告)号：US11908952B2

公开(公告)日：2024-02-20

申请号：US17840737

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Woo Seok Park ,  Dong Chan Suh ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78618

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

公开(公告)号：US11211495B2

公开(公告)日：2021-12-28

申请号：US16922464

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojin Jeong ,  Dong Il Bae ,  Geumjong Bae ,  Seungmin Song ,  Junggil Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20210091232A1

公开(公告)日：2021-03-25

申请号：US16953785

申请日：2020-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Woo Seok Park ,  Dong Chan Suh ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

公开(公告)号：US10916658B2

公开(公告)日：2021-02-09

申请号：US16894270

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  Dong Il Bae

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US10903324B2

公开(公告)日：2021-01-26

申请号：US16205851

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US10714617B2

公开(公告)日：2020-07-14

申请号：US16011785

申请日：2018-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  Dong Il Bae

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US10665723B2

公开(公告)日：2020-05-26

申请号：US16161765

申请日：2018-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min Song ,  Woo Seok Park ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02

Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.

公开(公告)号：US10347718B2

公开(公告)日：2019-07-09

申请号：US15877667

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L21/70 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/10 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.