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    Integrated circuit and standard cell library
    11.
    发明授权
    Integrated circuit and standard cell library 有权

    公开(公告)号：US10297596B2

    公开(公告)日：2019-05-21

    申请号：US15496507

    申请日：2017-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Deepak Sharma ,  Hyun-jong Lee ,  Raheel Azmat ,  Chul-hong Park ,  Sang-jun Park

    IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

    Integrated circuit devices
    12.
    发明授权
    Integrated circuit devices 有权

    公开(公告)号：US10249605B2

    公开(公告)日：2019-04-02

    申请号：US15655125

    申请日：2017-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kuchanuri Subhash ,  Rastogi Sidharth ,  Deepak Sharma ,  Chul-hong Park ,  Jae-seok Yang

    IPC: H01L27/02 ,  H01L23/528 ,  H01L27/118 ,  H01L27/11 ,  H01L27/105 ,  H03K19/00

    Abstract: An integrated circuit (IC) device includes at least one standard cell. The at least one standard cell includes: first and second active regions respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction; first and second gate lines extending parallel to each other in a second direction perpendicular to the first direction across the first and second active regions, a first detour interconnection structure configured to electrically connect the first gate line with the second gate line; and a second detour interconnection structure configured to electrically connect the second gate line with the first gate line. The first and second detour interconnection structures include a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via.

    Integrated circuit and standard cell library
    16.
    发明授权
    Integrated circuit and standard cell library 有权

    公开(公告)号：US11316032B2

    公开(公告)日：2022-04-26

    申请号：US16887331

    申请日：2020-05-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Deepak Sharma ,  Hyun-jong Lee ,  Raheel Azmat ,  Chul-hong Park ,  Sang-jun Park

    IPC: H01L29/66 ,  H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238

    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

    Logic cell including single layer via contact and deep via contact
    19.
    发明授权
    Logic cell including single layer via contact and deep via contact 有权

    公开(公告)号：US10177087B2

    公开(公告)日：2019-01-08

    申请号：US15493279

    申请日：2017-04-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Vincent Chun Fai Lau ,  Jung-ho Do ,  Byung-sung Kim ,  Chul-hong Park

    IPC: H01L27/088 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

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