公开(公告)号：US10665295B2

公开(公告)日：2020-05-26

申请号：US16191717

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lava Kumar Pulluru ,  Parvinder Kumar Rana ,  Akash Kumar Gupta ,  Gayatri Nair

IPC: G11C11/419 ,  G11C11/4097 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/418

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

公开(公告)号：US12205636B2

公开(公告)日：2025-01-21

申请号：US18163584

申请日：2023-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poornima Venkatasubramanian ,  Pushp Khatter ,  Lava Kumar Pulluru ,  Manish Chandra Joshi ,  Ved Prakash ,  Anurag Kumar ,  Surendra Deshmukh

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

公开(公告)号：US20240321324A1

公开(公告)日：2024-09-26

申请号：US18375805

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poornima Venkatasubramanian ,  Gopi Sunanth Kumar Gogineni ,  Puneet Suri ,  Lava Kumar Pulluru ,  Karthikeyan Somashekara ,  Manish Chandra Joshi

IPC: G11C7/04 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/04 ,  G11C7/14 ,  G11C7/222

Abstract: A memory device, includes a voltage and temperature sensing circuit configured to generate a Pull Down (PD) signal that varies based on upon at least one of a voltage and temperature at the memory device; and primary pull down paths provided with secondary pull down paths, wherein the primary pull down paths are provided separately at a Dummy Read Bit line (DRBL) and a Dummy Global Read Bit line (DGRBL), wherein the secondary pull down paths are provided separately for the DRBL and the DGRBL parallel to the respective primary pull down paths. The voltage and temperature sensing circuit is configured to perform at least one of: controlling at least one of the secondary pull down paths based on a voltage of the PD signal; varying a discharge time of at least one of the dummy bit-lines based on the voltage of the PD signal; and generating an early reset signal at one of a high temperature condition and a high voltage condition based on the voltage of the PD signal.

公开(公告)号：US20220366970A1

公开(公告)日：2022-11-17

申请号：US17815003

申请日：2022-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Ankur Gupta ,  Parvinder Kumar Rana

IPC: G11C11/419

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

公开(公告)号：US20220108744A1

公开(公告)日：2022-04-07

申请号：US16952712

申请日：2020-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lava Kumar Pulluru ,  Ankur Gupta ,  Parvinder Kumar Rana

IPC: G11C11/419

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

公开(公告)号：US10147493B2

公开(公告)日：2018-12-04

申请号：US15665988

申请日：2017-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Parvinder Kumar Rana ,  Lava Kumar Pulluru ,  Manish Chandra Joshi

IPC: G11C16/32 ,  G11C16/08

Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.