知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.022 seconds)

    Methods of manufacturing semiconductor devices
    11.
    发明授权
    Methods of manufacturing semiconductor devices 有权

    公开(公告)号：US10777449B2

    公开(公告)日：2020-09-15

    申请号：US16242483

    申请日：2019-01-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Shin Jang ,  Woo-Kyung You ,  Kyu-Hee Han ,  Jong-Min Baek ,  Viet Ha Nguyen ,  Byung-Hee Kim

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

    Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.

    Semiconductor device
    14.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11776906B2

    公开(公告)日：2023-10-03

    申请号：US17480615

    申请日：2021-09-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jangho Lee ,  Jongmin Baek ,  Wookyung You ,  Kyu-Hee Han ,  Suhyun Bark

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L23/5283 ,  H01L21/76832 ,  H01L21/76843 ,  H01L23/5226

    Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

    Semiconductor device and method of fabricating the same
    15.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US11348827B2

    公开(公告)日：2022-05-31

    申请号：US16798789

    申请日：2020-02-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Jin Kang ,  Jong Min Baek ,  Woo Kyung You ,  Kyu-Hee Han ,  Han Seong Kim ,  Jang Ho Lee ,  Sang Shin Jang

    IPC: H01L21/768 ,  H01L23/48

    Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

    Semiconductor devices and methods of manufacturing the same
    16.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US11037872B2

    公开(公告)日：2021-06-15

    申请号：US16374901

    申请日：2019-04-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyu-Hee Han ,  Jong-Min Baek ,  Hoon-Seok Seo ,  Sang-Hoon Ahn ,  Woo-Jin Lee

    IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02

    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.

    Semiconductor device and method of manufacturing the same
    17.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US10943824B2

    公开(公告)日：2021-03-09

    申请号：US16411439

    申请日：2019-05-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woojin Lee ,  Hoon Seok Seo ,  Sanghoon Ahn ,  Kyu-Hee Han

    IPC: H01L23/528 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

    Semiconductor device
    18.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10566284B2

    公开(公告)日：2020-02-18

    申请号：US16027484

    申请日：2018-07-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Kwan Kim ,  Sanghoon Ahn ,  Kyu-Hee Han ,  JaeWha Park ,  Heesook Park

    IPC: H01L23/532 ,  H01L23/522

    Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.

    Semiconductor device including air-gap
    19.
    发明授权
    Semiconductor device including air-gap 有权

    公开(公告)号：US10090381B2

    公开(公告)日：2018-10-02

    申请号：US15628675

    申请日：2017-06-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin Baek ,  Vietha Nguyen ,  Wookyung You ,  Sangshin Jang ,  Byunghee Kim ,  Kyu-Hee Han

    IPC: H01L21/70 ,  H01L21/76 ,  H01L29/06

    Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.

    SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME
    20.
    发明申请
    SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME 有权
    具有电极的半导体器件及其制造方法

    公开(公告)号：US20150155233A1

    公开(公告)日：2015-06-04

    申请号：US14490964

    申请日：2014-09-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyu-Hee Han ,  Pil-Kyu Kang ,  Taejin Yim ,  Naein Lee

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.

    Abstract translation: 本发明构思提供半导体器件及其制造方法。 该方法包括在基板上形成包括多个电介质层的金属间介电层，形成垂直贯穿金属间介电层和基板的通孔，向至少一个表面提供碳，例如包括 通过通孔露出的多个电介质层中的碳，形成覆盖通路孔的内表面的通孔电介质层，以及形成由通路孔中的通孔电介质层包围的贯通电极。

Patent Agency Ranking