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    Semiconductor memory devices and methods of fabricating the same
    11.
    发明授权
    Semiconductor memory devices and methods of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09379123B2

    公开(公告)日：2016-06-28

    申请号：US14848423

    申请日：2015-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

    IPC: H01L21/764 ,  H01L27/115 ,  H01L29/423

    CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

    Abstract translation: 提供一种半导体存储器件及其制造方法。 半导体存储器件可以包括半导体衬底，其具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，设置在第一区域上的栅电极以跨越有源区域， 存储图案，设置在所述栅电极和所述有源区之间，阻挡绝缘层，设置在所述栅电极和所述电荷存储图案之间并在所述第一沟槽上延伸以限定所述第一沟槽中的第一气隙，以及间隔开的绝缘图案 从第二沟槽的底表面到第二沟槽中限定第二气隙。

    Methods of fabricating semiconductor devices and devices fabricated thereby
    12.
    发明授权
    Methods of fabricating semiconductor devices and devices fabricated thereby 有权
    制造半导体器件的方法和由此制造的器件

    公开(公告)号：US09378979B2

    公开(公告)日：2016-06-28

    申请号：US14503498

    申请日：2014-10-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang Sim ,  Jinhyun Shin

    IPC: H01L21/302 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L27/115

    CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11531

    Abstract: Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided.

    Abstract translation: 提供制造半导体器件的方法包括执行两个光刻工艺和两个间隔工艺，使得图案形成为具有小于光刻工艺限制的间距。 此外，通过执行一次光刻工艺同时限定线和焊盘部分，因此不需要执行用于形成焊盘部分的附加光刻工艺。 还提供了相关设备。

    Semiconductor device and method of manufacturing the same
    13.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08946804B2

    公开(公告)日：2015-02-03

    申请号：US13852578

    申请日：2013-03-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang Sim

    IPC: H01L29/788 ,  H01L21/76

    CPC classification number: H01L27/0207 ,  H01L27/11519 ,  H01L27/11524

    Abstract: A semiconductor device, and a method of fabrication the same, include selection gate patterns extending in a first direction on a substrate, cell gate patterns extending in parallel in the first direction between the selection gate patterns adjacent to each other, and contact pads connected to first end parts of the cell gate patterns, respectively. An insulating layer covers the selection gate patterns, the cell gate patterns, and the contact pads. The insulating layer includes a void or seam between the contact pads. A filling insulating layer fills the void or seam in the insulating layer.

    Abstract translation: 半导体器件及其制造方法包括在衬底上沿第一方向延伸的选择栅极图案，在彼此相邻的选择栅极图案之间沿第一方向平行延伸的单元栅极图案以及连接到 分别是单元栅极图案的第一端部分。 绝缘层覆盖选择栅极图案，单元栅极图案和接触垫。 绝缘层包括接触垫之间的空隙或接缝。 填充绝缘层填充绝缘层中的空隙或接缝。

    String floating gates with air gaps in between
    14.
    发明授权
    String floating gates with air gaps in between 有权
    字符串浮动闸门之间有气隙

    公开(公告)号：US08796752B2

    公开(公告)日：2014-08-05

    申请号：US14019698

    申请日：2013-09-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang Sim

    IPC: H01L29/92 ,  H01L21/8238

    CPC classification number: H01L29/788 ,  H01L21/76229 ,  H01L21/764

    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.

    Abstract translation: 一种制造半导体器件的方法包括形成彼此间隔开第一距离的多个串，每个串包括在第二预栅结构之间间隔第二距离小于第一距离的第一预栅极结构，形成第一绝缘层 覆盖第一和第二预选栅极结构，形成绝缘层结构以填充串之间的空间，形成牺牲层图案以部分地填充第一和第二预选栅结构之间的空间，去除未覆盖的第一绝缘层的一部分 通过所述牺牲层图案以形成第一绝缘层图案，使未被所述第一绝缘层图案覆盖的所述第一和第二预选栅极结构的部分与导电层反应以形成栅极结构，并且在所述栅极结构上形成覆盖层 在门结构之间形成气隙。

    Semiconductor memory devices
    15.
    发明授权
    Semiconductor memory devices 有权
    半导体存储器件

    公开(公告)号：US08759900B2

    公开(公告)日：2014-06-24

    申请号：US13742557

    申请日：2013-01-16

    Applicant: Samsung Electronics, Co., Ltd.

    Inventor： Jae-Hwang Sim

    IPC: H01L29/788

    CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/228 ,  H01L29/7881 ,  H01L29/792 ,  H01L43/02

    Abstract: A semiconductor memory device includes a substrate including a cell region and a peripheral region, word lines on the substrate of the cell region, each of the word lines including a charge storing part and a control gate electrode sequentially stacked, and a peripheral gate pattern on the substrate of the peripheral region. Each of the control gate electrode and the peripheral gate pattern includes a high-carbon semiconductor pattern and a low-carbon semiconductor pattern, the low-carbon semiconductor pattern being on the high-carbon semiconductor pattern.

    Abstract translation: 半导体存储器件包括：包括单元区域和外围区域的衬底，单元区域的衬底上的字线，每个字线包括依次堆叠的电荷存储部分和控制栅电极;以及周边栅极图案， 外围区域的基板。 控制栅电极和外围栅极图案中的每一个包括高碳半导体图案和低碳半导体图案，低碳半导体图案位于高碳半导体图案上。

    SEMICONDUCTOR DEVICES HAVING AIRGAPS AND METHODS OF MANUFACTURING THE SAME
    17.
    发明申请
    SEMICONDUCTOR DEVICES HAVING AIRGAPS AND METHODS OF MANUFACTURING THE SAME 审中-公开
    具有AIRGAPS的半导体器件及其制造方法

    公开(公告)号：US20150228660A1

    公开(公告)日：2015-08-13

    申请号：US14692197

    申请日：2015-04-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

    IPC: H01L27/115 ,  H01L29/06 ,  H01L21/764

    CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

    Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

    Abstract translation: 公开了非易失性存储器件及其制造方法。 非易失性存储器件包括限定衬底中的有源部分和设置在衬底上的栅极结构的器件隔离图案。 有源部分在第一方向上彼此间隔开，并且在垂直于第一方向的第二方向上延伸。 栅极结构在第二方向上彼此间隔开并且在第一方向上延伸。 每个器件隔离图案包括第一气隙，并且第一气隙的顶表面和底表面中的每一个在沿着第二方向截取的截面图中具有波形。

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