公开(公告)号：US20220013538A1

公开(公告)日：2022-01-13

申请号：US17158494

申请日：2021-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： So Hyeon Lee ,  Sung Su Moon ,  Jae Duk Lee ,  Ik-Hyung Joo

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11526

Abstract: A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.

公开(公告)号：US09716104B2

公开(公告)日：2017-07-25

申请号：US14987835

申请日：2016-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  HanMei Choi

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11568

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US11538533B2

公开(公告)日：2022-12-27

申请号：US17233858

申请日：2021-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gu Yeon Han ,  Jin-Kyu Kang ,  Rae Young Lee ,  Se Jun Park ,  Jae Duk Lee

IPC: G11C7/12 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C16/30 ,  G11C16/24 ,  G11C16/32

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

公开(公告)号：US10903234B2

公开(公告)日：2021-01-26

申请号：US16275756

申请日：2019-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Gn Yun ,  Jae Duk Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.

公开(公告)号：US10468433B2

公开(公告)日：2019-11-05

申请号：US16015702

申请日：2018-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Kim ,  Young Jin Jung ,  Jae Duk Lee

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L27/11578 ,  H01L27/11568 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/11595 ,  H01L27/11526 ,  H01L27/11521 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/1156 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/02 ,  H01L29/10 ,  H01L29/423 ,  H01L21/033 ,  H01L21/311 ,  H01L29/66 ,  H01L29/792

Abstract: A three-dimensional semiconductor device is provided including main separation structures disposed on a substrate, and extending in a first direction, parallel to a surface of the substrate; gate electrodes disposed between the main separation structures; a first secondary separation structure penetrating through the gate electrodes, between the main separation structures, and including a first linear portion and a second linear portion, having end portions opposing each other; and second secondary separation structures disposed between the first secondary separation structure and the main separation structures, and penetrating through the gate electrodes. The second secondary separation structures have end portions opposing each other between the second linear portion and the main separation structures.