公开(公告)号：US20220384480A1

公开(公告)日：2022-12-01

申请号：US17819355

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  SangJun Hong

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575

Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

公开(公告)号：US11856773B2

公开(公告)日：2023-12-26

申请号：US17176398

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Seo ,  Euntaek Jung ,  Byoungil Lee ,  Seul Lee ,  Joonhee Lee ,  Changdae Jung ,  Bonghyun Choi ,  Sejie Takaki

IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

公开(公告)号：US11839084B2

公开(公告)日：2023-12-05

申请号：US17825619

申请日：2022-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  JiHye Yun

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L21/28 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H01L23/522 ,  H10B41/50 ,  H10B43/50 ,  H10B69/00 ,  H01L29/66 ,  H10B43/30

CPC classification number: H10B43/27 ,  H01L21/28525 ,  H01L21/76868 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/66833 ,  H10B41/50 ,  H10B43/30 ,  H10B43/50 ,  H10B69/00

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

公开(公告)号：US11785768B2

公开(公告)日：2023-10-10

申请号：US17360349

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  Joongshik Shin ,  Dongyoun Shin

IPC: H01L27/11519 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.

公开(公告)号：US20230014037A1

公开(公告)日：2023-01-19

申请号：US17690154

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  Jaeho Kim ,  Joonsung Kim ,  Jiwon Kim ,  Sukkang Sung ,  Sangdon Lee ,  Jong-Min Lee

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  G11C16/04

Abstract: A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

公开(公告)号：US11424259B2

公开(公告)日：2022-08-23

申请号：US17011051

申请日：2020-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  Joongshik Shin

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11548 ,  H01L29/10 ,  H01L29/423 ,  H01L29/792

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same are provided. A memory device may include a semiconductor layer including first and second regions, first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer, and second vertical structures on the second region and extending in the first direction. The first vertical structure may include a vertical semiconductor pattern extending in the first direction and in contact with the semiconductor layer, and a first data storage pattern surrounding the vertical semiconductor pattern. The second vertical structure may include an insulation structure extending in the first direction and in contact with the semiconductor layer, and a second data storage pattern surrounding the insulation structure.

公开(公告)号：US11348942B2

公开(公告)日：2022-05-31

申请号：US16999511

申请日：2020-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  JiHye Yun

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11548 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/115

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

公开(公告)号：US10777565B2

公开(公告)日：2020-09-15

申请号：US16017013

申请日：2018-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  Joongshik Shin

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11548 ,  H01L29/10 ,  H01L29/423

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same are provided. A memory device may include a semiconductor layer including first and second regions, first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer, and second vertical structures on the second region and extending in the first direction. The first vertical structure may include a vertical semiconductor pattern extending in the first direction and in contact with the semiconductor layer, and a first data storage pattern surrounding the vertical semiconductor pattern. The second vertical structure may include an insulation structure extending in the first direction and in contact with the semiconductor layer, and a second data storage pattern surrounding the insulation structure.

公开(公告)号：US10593393B2

公开(公告)日：2020-03-17

申请号：US16502943

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JoongShik Shin ,  Byoungil Lee ,  Hyunmog Park ,  Euntaek Jung

IPC: H01L29/76 ,  G11C11/408 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  G11C8/08 ,  G11C8/12 ,  G11C11/06 ,  H01L21/8239 ,  H01L23/528

Abstract: A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.