公开(公告)号：US11437397B2

公开(公告)日：2022-09-06

申请号：US16139775

申请日：2018-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  SangJun Hong

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L29/423

Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

公开(公告)号：US10964714B2

公开(公告)日：2021-03-30

申请号：US16259086

申请日：2019-01-28

Applicant: Samsung Electronics Co., Ltd

Inventor： Geunwon Lim ,  SangJun Hong ,  Seokcheon Baek

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.

公开(公告)号：US11616076B2

公开(公告)日：2023-03-28

申请号：US17216867

申请日：2021-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  SangJun Hong ,  Seokcheon Baek

IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.

公开(公告)号：US20220384480A1

公开(公告)日：2022-12-01

申请号：US17819355

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  SangJun Hong

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575

Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

公开(公告)号：US20190393238A1

公开(公告)日：2019-12-26

申请号：US16259086

申请日：2019-01-28

Applicant: Samsung Electronics Co., Ltd

Inventor： Geunwon LIM ,  SangJun Hong ,  Seokcheon Baek

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423 ,  H01L23/522

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.