公开(公告)号：US11437397B2

公开(公告)日：2022-09-06

申请号：US16139775

申请日：2018-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  SangJun Hong

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L29/423

Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

公开(公告)号：US11430808B2

公开(公告)日：2022-08-30

申请号：US16895364

申请日：2020-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Beyounghyun Koh ,  Yongjin Kwon ,  Kangmin Kim ,  Jaehoon Shin ,  JoongShik Shin ,  Sungsoo Ahn ,  Seunghwan Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

公开(公告)号：US11063057B2

公开(公告)日：2021-07-13

申请号：US16152605

申请日：2018-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  Dongyoun Shin

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.

公开(公告)号：US10777572B2

公开(公告)日：2020-09-15

申请号：US16192859

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  JiHye Yun

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11548

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

公开(公告)号：US12232323B2

公开(公告)日：2025-02-18

申请号：US18515536

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  JiHye Yun

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H01L23/522 ,  H01L29/66 ,  H01L49/02 ,  H10B41/40 ,  H10B41/50 ,  H10B43/10 ,  H10B43/30 ,  H10B43/50 ,  H10B69/00

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

公开(公告)号：US20220384480A1

公开(公告)日：2022-12-01

申请号：US17819355

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  SangJun Hong

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575

Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

公开(公告)号：US20240090224A1

公开(公告)日：2024-03-14

申请号：US18515536

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek JUNG ,  JoongShik Shin ,  JiHye YUN

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L21/28525 ,  H01L21/76868 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H01L23/5226 ,  H01L23/5283

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

公开(公告)号：US10373673B2

公开(公告)日：2019-08-06

申请号：US15614714

申请日：2017-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JoongShik Shin ,  Byoungil Lee ,  Hyunmog Park ,  Euntaek Jung

IPC: H01L29/76 ,  G11C11/408 ,  G11C8/08 ,  G11C8/12 ,  G11C11/06 ,  H01L21/8239 ,  H01L23/528 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

公开(公告)号：US11839084B2

公开(公告)日：2023-12-05

申请号：US17825619

申请日：2022-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  JiHye Yun

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L21/28 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H01L23/522 ,  H10B41/50 ,  H10B43/50 ,  H10B69/00 ,  H01L29/66 ,  H10B43/30

CPC classification number: H10B43/27 ,  H01L21/28525 ,  H01L21/76868 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/66833 ,  H10B41/50 ,  H10B43/30 ,  H10B43/50 ,  H10B69/00

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

公开(公告)号：US11348942B2

公开(公告)日：2022-05-31

申请号：US16999511

申请日：2020-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik Shin ,  JiHye Yun

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11548 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/115

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.