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    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230024655A1

    公开(公告)日：2023-01-26

    申请号：US17858388

    申请日：2022-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangdon LEE ,  Joonsung KIM ,  Jiwon KIM ,  Jaeho KIM ,  Sukkang SUNG ,  Jong-Min LEE ,  Euntaek JUNG

    IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

    Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device may include a stack structure extending in a first direction and including gate electrodes vertically stacked on a substrate, selection structures horizontally spaced apart on the stack structure, an upper isolation structure between the selection structure and extending in the first direction on the stack structure, and vertical structures penetrating the stack structure and the selection structures. The vertical structures include first vertical structures arranged along the first direction and penetrating portions of the upper isolation structure. Each selection structure includes a selection gate electrode and a horizontal dielectric pattern that surrounds top, bottom, and sidewall surfaces of the selection gate electrode. Each selection gate electrode includes a line part extending in the first direction, and an electrode part vertically protruding from the line part and surrounding at least a portion of each first vertical structure.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210327892A1

    公开(公告)日：2021-10-21

    申请号：US17360349

    申请日：2021-06-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euntaek JUNG ,  JoongShik SHIN ,  Dongyoun SHIN

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519

    Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    4.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240315034A1

    公开(公告)日：2024-09-19

    申请号：US18507258

    申请日：2023-11-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euntaek JUNG ,  Sukkang SUNG

    IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

    CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device includes a substrate, stacking structure, first selection gate electrode, memory gate electrodes stacked on the substrate; a first channel structure penetrating the stacking structure and extending along one direction, a first channel layer, a first dielectric layer between the first channel layer and stacking structure, a channel pad on the first channel layer; an insulation pattern above the stacking structure, a penetration portion exposing some of the first channel structure, a second selection gate electrode on the insulation pattern, a second channel structure extending in one direction penetrating the second selection gate electrode, a contact pattern connected to the first channel structure including a first portion within the penetration portion on an upper surface of the channel pad, and a second portion protruding toward the substrate to include a recess in the channel pad and the first dielectric layer inside a bottom surface of the first portion.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    5.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230012115A1

    公开(公告)日：2023-01-12

    申请号：US17570874

    申请日：2022-01-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaeho KIM ,  Jiwon KIM ,  Joonsung KIM ,  Sukkang SUNG ,  Sangdon LEE ,  Jong-Min LEE ,  Euntaek JUNG

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

    Abstract: A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    7.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240074203A1

    公开(公告)日：2024-02-29

    申请号：US18357401

    申请日：2023-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euntaek JUNG ,  Sukkang SUNG

    IPC: H10B43/50 ,  H10B43/27

    CPC classification number: H10B43/50 ,  H10B43/27

    Abstract: A semiconductor device may include a peripheral circuit structure including cell region and an outside region, a cell structure on the cell region, an outside structure on the outside region, and an insulating layer. The outside structure may include a dummy stacked structure, a through electrode penetrating the dummy stacked structure and connected to the peripheral circuit structure, and a dummy vertical structure adjacent to the through electrode and penetrating at least a portion of the dummy stacked structure. The insulating layer may be between the dummy stacked structure and the peripheral circuit structure. The dummy stacked structure may include an upper dummy stacked structure on a lower dummy stacked structure. The upper dummy stacked structure may include upper dummy patterns stacked on the lower dummy stacked structure. The lower dummy stacked structure may include lower dummy patterns stacked on the outside region.

    VERTICAL NON-VOLATILE MEMORY DEVICE
    8.
    发明申请
    VERTICAL NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20230109996A1

    公开(公告)日：2023-04-13

    申请号：US17955696

    申请日：2022-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghoon SON ,  Sukkang SUNG ,  Sangdon LEE ,  Euntaek JUNG

    IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

    Abstract: A vertical non-volatile memory device includes, a substrate, a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the substrate, the vertical direction being perpendicular to a surface of the substrate, a plurality of insulating layers between the gate lines, a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in a horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole, the horizontal direction being horizontal to the surface of the substrate, and a contact electrode at the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    10.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190333922A1

    公开(公告)日：2019-10-31

    申请号：US16152605

    申请日：2018-10-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euntaek JUNG ,  JoongShik SHIN ,  Dongyoun SHIN

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157

    Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.

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