公开(公告)号：US11164887B2

公开(公告)日：2021-11-02

申请号：US16749110

申请日：2020-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yujin Seo ,  Byoungil Lee ,  Subin Kang ,  Jimo Gu

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A vertical memory device includes channels on a substrate, a channel connecting pattern, gate electrodes, and an etch stop pattern and a blocking pattern sequentially stacked. The channels extend in a first direction perpendicular to an upper surface of the substrate. The channel connecting pattern extends in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the channels. The gate electrodes are spaced apart from each other in the first direction on the channel connecting pattern, and extend in the second direction to surround the channels. The etch stop pattern and the blocking pattern are sequentially stacked in a third direction parallel to the upper surface of the substrate and crossing the second direction on an end portion of the channel connecting pattern in the third direction, and include different materials from each other.

公开(公告)号：US11856773B2

公开(公告)日：2023-12-26

申请号：US17176398

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Seo ,  Euntaek Jung ,  Byoungil Lee ,  Seul Lee ,  Joonhee Lee ,  Changdae Jung ,  Bonghyun Choi ,  Sejie Takaki

IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

公开(公告)号：US11792990B2

公开(公告)日：2023-10-17

申请号：US17514331

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yujin Seo ,  Byoungil Lee ,  Subin Kang ,  Jimo Gu

IPC: H01L27/11582 ,  H10B43/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical memory device includes channels on a substrate, a channel connecting pattern, gate electrodes, and an etch stop pattern and a blocking pattern sequentially stacked. The channels extend in a first direction perpendicular to an upper surface of the substrate. The channel connecting pattern extends in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the channels. The gate electrodes are spaced apart from each other in the first direction on the channel connecting pattern, and extend in the second direction to surround the channels. The etch stop pattern and the blocking pattern are sequentially stacked in a third direction parallel to the upper surface of the substrate and crossing the second direction on an end portion of the channel connecting pattern in the third direction, and include different materials from each other.

公开(公告)号：US20210375920A1

公开(公告)日：2021-12-02

申请号：US17176398

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Seo ,  Euntaek Jung ,  Byoungil Lee ,  Seul Lee ,  Joonhee Lee ,  Changdae Jung ,  Bonghyun Choi ,  Sejie Takaki

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11519

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

公开(公告)号：US11737273B2

公开(公告)日：2023-08-22

申请号：US17146564

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungwoo Nam ,  Byoungil Lee ,  Yujin Seo

IPC: H01L27/11582 ,  H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: 3D semiconductor memory devices may include a horizontal structure that may be on an upper surface of a substrate and may include first and second horizontal patterns sequentially stacked on the upper surface of the substrate, a stack structure including electrodes stacked on the horizontal structure, a vertical pattern extending through the electrodes and connected to the first horizontal pattern, and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode may have first inner sidewalls facing each other with the separation structure interposed therebetween. The second horizontal pattern may have second inner sidewalls facing each other with the separation structure interposed therebetween. A maximum distance between the first inner sidewalls in the first direction may be less than a maximum distance between the second inner sidewalls in the first direction.

公开(公告)号：US20210296359A1

公开(公告)日：2021-09-23

申请号：US17146564

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGWOO Nam ,  Byoungil Lee ,  Yujin Seo

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11526

Abstract: 3D semiconductor memory devices may include a horizontal structure that may be on an upper surface of a substrate and may include first and second horizontal patterns sequentially stacked on the upper surface of the substrate, a stack structure including electrodes stacked on the horizontal structure, a vertical pattern extending through the electrodes and connected to the first horizontal pattern, and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode may have first inner sidewalls facing each other with the separation structure interposed therebetween. The second horizontal pattern may have second inner sidewalls facing each other with the separation structure interposed therebetween. A maximum distance between the first inner sidewalls in the first direction may be less than a maximum distance between the second inner sidewalls in the first direction.