公开(公告)号：US11856773B2

公开(公告)日：2023-12-26

申请号：US17176398

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Seo ,  Euntaek Jung ,  Byoungil Lee ,  Seul Lee ,  Joonhee Lee ,  Changdae Jung ,  Bonghyun Choi ,  Sejie Takaki

IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

公开(公告)号：US20210225869A1

公开(公告)日：2021-07-22

申请号：US17021627

申请日：2020-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sejie Takaki

IPC: H01L27/11582 ,  H01L21/311 ,  H01L27/11573

Abstract: A memory device includes a substrate, a stacked structure, channel layers, and separation layers. The substrate includes a first layer, a second layer on the first layer, and a third layer on the second layer/ The stacked structure including electrode layers stacked on the substrate. The channel layers extend in a direction perpendicular to an upper surface of the substrate, to penetrate through the stacked structure and to contact with the second layer in a direction horizontal to the upper surface of the substrate. The separation layers divide the stacked structure into unit structures. A first boundary between the first layer and the second layer below one or more of the separation layers is disposed to be lower than a second boundary between the first layer and the second layer that is located between an adjacent two channel layers.

公开(公告)号：US11812617B2

公开(公告)日：2023-11-07

申请号：US17214879

申请日：2021-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sejie Takaki

IPC: H10B43/50 ,  H01L23/535 ,  H01L25/065 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L23/535 ,  H01L25/0657 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor device includes a memory stack on a substrate, the memory stack including gate electrodes, insulating layers and mold layers, the mold layers being disposed at the same levels as the gate electrodes in a through electrode area, a channel structure extending vertically through the gate electrodes in a cell array area, and a dam structure disposed between the isolation insulating layers and surrounding the through electrode area in a top view. The dam structure includes a dam insulating layer having a dam shape, an inner insulating layer inside the dam insulating layer, and an outer insulating layer outside the dam insulating layer. The inner insulating layer includes first protrusions protruding in a horizontal direction, and the outer insulating layer includes second protrusions protruding in the horizontal direction.

公开(公告)号：US11805654B2

公开(公告)日：2023-10-31

申请号：US17207208

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sejie Takaki ,  JoonHee Lee

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper.

公开(公告)号：US11716854B2

公开(公告)日：2023-08-01

申请号：US17024105

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Woosung Yang ,  Sejie Takaki

IPC: H10B43/40 ,  G11C7/18 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/40 ,  G11C7/18 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.

公开(公告)号：US20210375920A1

公开(公告)日：2021-12-02

申请号：US17176398

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Seo ,  Euntaek Jung ,  Byoungil Lee ,  Seul Lee ,  Joonhee Lee ,  Changdae Jung ,  Bonghyun Choi ,  Sejie Takaki

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11519

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.