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    Real time automatic and background calibration at embedded duty cycle correlation
    13.
    发明授权
    Real time automatic and background calibration at embedded duty cycle correlation 有权
    嵌入式占空比相关的实时自动和背景校准

    公开(公告)号：US09148135B2

    公开(公告)日：2015-09-29

    申请号：US13532881

    申请日：2012-06-26

    Applicant: Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    Inventor： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC: G06F1/00 ,  H03K5/156 ,  G06F1/08

    CPC classification number: H03K5/1565 ,  G06F1/08

    Abstract: The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

    Abstract translation: 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。

    PLL with oscillator PVT compensation
    14.
    发明授权
    PLL with oscillator PVT compensation 有权
    PLL振荡器PVT补偿

    公开(公告)号：US08963649B2

    公开(公告)日：2015-02-24

    申请号：US13731687

    申请日：2012-12-31

    Applicant: Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    Inventor： Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC: H03L1/00 ,  H03L7/06 ,  H03B5/10

    CPC classification number: H03L1/00 ,  H03B5/10 ,  H03L7/06 ,  H03L7/099 ,  H03L7/0992

    Abstract: A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

    Abstract translation: 压控振荡器（VCO）包括电流控制振荡器，电压 - 电流转换器和感测电路。 感测电路包括延迟单元，并且感测电路被配置为响应于延迟单元的时间延迟而产生多个补偿控制信号。 电压 - 电流转换器被配置为响应于VCO控制信号和多个补偿控制信号而产生电流信号。 电流控制振荡器被配置为响应于当前信号产生振荡信号。

    Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation
    15.
    发明申请
    Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation 有权
    嵌入式占空比相关的实时自动和背景校准

    公开(公告)号：US20130342252A1

    公开(公告)日：2013-12-26

    申请号：US13532881

    申请日：2012-06-26

    Applicant: Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    Inventor： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC: H03K3/017

    CPC classification number: H03K5/1565 ,  G06F1/08

    Abstract: The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

    Abstract translation: 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。

    High speed communication interface with an adaptive swing driver to reduce power consumption
    17.
    发明授权
    High speed communication interface with an adaptive swing driver to reduce power consumption 有权

    公开(公告)号：US08410818B1

    公开(公告)日：2013-04-02

    申请号：US13372978

    申请日：2012-02-14

    Applicant: Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    Inventor： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC: H03K19/094

    CPC classification number: H03K3/012 ,  H03K19/0013 ,  H03K19/018521

    Abstract: A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

    Synthesis subband filter process and apparatus
    18.
    发明授权
    Synthesis subband filter process and apparatus 有权
    合成子带滤波过程及装置

    公开(公告)号：US07580843B2

    公开(公告)日：2009-08-25

    申请号：US11430702

    申请日：2006-05-08

    Applicant: Chih-Hsien Chang ,  Chih-Wei Hung ,  Hsien-Ming Tsai

    Inventor： Chih-Hsien Chang ,  Chih-Wei Hung ,  Hsien-Ming Tsai

    IPC: G10L19/00 ,  G10L13/00 ,  G06F17/14

    CPC classification number: G10L19/0208

    Abstract: A synthesis subband filter apparatus is provided. The apparatus is used for processing 18 sets of signals which each includes 32 subband sampling signals in accordance with a specification providing 512 window coefficients. The apparatus includes a processor for processing the 18 sets of signals in sequence. The processor further includes a converting module and a generating module. The converting module is used for converting the 32 subband sampling signals of the set of signals being processed into 32 converted vectors by use of 32-points discrete cosine transform (DCT), and writing the 32 converted vectors into 512 default vectors with a first-in, first-out queue. The generating module is used for generating 32 pulse code modulation (PCM) signals, relative to the set of signals being processed according to a set of synthesis formulae proposed in this invention.

    Abstract translation: 提供合成子带滤波器装置。 该装置用于处理根据提供512个窗系数的规范的18组信号，每组信号包括32个子带采样信号。 该装置包括用于依次处理18组信号的处理器。 处理器还包括转换模块和生成模块。 转换模块用于通过使用32点离散余弦变换（DCT）将被处理的信号组的32个子带采样信号转换为32个转换的矢量，并将32个转换的矢量写入512个默认矢量， 在，先出队列。 生成模块用于产生32个脉码调制（PCM）信号，相对于根据本发明中提出的一组合成公式处理的信号集合。

    Optical sub-assembly module for suppressing optical back-reflection and effectively guiding light from light source to optical waveguide
    19.
    发明授权
    Optical sub-assembly module for suppressing optical back-reflection and effectively guiding light from light source to optical waveguide 失效
    用于抑制光学背反射并有效地将光从光源引导到光波导的光学子组件模块

    公开(公告)号：US06945710B2

    公开(公告)日：2005-09-20

    申请号：US10341477

    申请日：2003-01-10

    Applicant: Wen-Tzung Chen ,  Chien-Cheng Yang ,  Chun-Chieh Chang ,  Chun-Te Lee ,  Chih-Hsien Chang ,  Cheng-Ta Chen ,  Bao-Jen Pong

    Inventor： Wen-Tzung Chen ,  Chien-Cheng Yang ,  Chun-Chieh Chang ,  Chun-Te Lee ,  Chih-Hsien Chang ,  Cheng-Ta Chen ,  Bao-Jen Pong

    IPC: G02B6/42 ,  G02B6/26

    CPC classification number: G02B6/4207

    Abstract: An optical sub-assembly (OSA) module for suppressing optical back-reflection and effectively guiding light from a light source to an optical waveguide is disclosed. The module comprises a light source for emitting light to said optical waveguide and at least one light transmitting element installed between said light source and said optical waveguide. The at least one light transmitting element is arranged to have a configuration for avoiding light to reflect back to the light source and to cause a light beam from said light source to point to said core of said optical waveguide. Thereby, the working distance is increased, and the assembling process of the OSA module is simplified. This new optical design scheme will greatly improve the optical characteristics of an OSA module, increase the optical transceiver propagation distance, and reduce the difficulty of OSA assembly process.

    Abstract translation: 公开了一种用于抑制光学背反射并有效地将光从光源引导到光波导的光学子组件（OSA）模块。 该模块包括用于向所述光波导发射光的光源和安装在所述光源和所述光波导之间的至少一个光传输元件。 所述至少一个光传输元件被布置成具有用于避免光反射回光源并使来自所述光源的光束指向所述光波导的所述芯的构造。 因此，工作距离增加，并且简化了OSA模块的组装过程。 这种新的光学设计方案将大大提高OSA模块的光学特性，增加光收发器的传播距离，降低OSA装配过程的难度。

    Control device for maintaining a chemical mechanical polishing machine in a wet mode
    20.
    发明授权
    Control device for maintaining a chemical mechanical polishing machine in a wet mode 有权
    控制装置，用于在湿式模式下保持化学机械抛光机

    公开(公告)号：US6099386A

    公开(公告)日：2000-08-08

    申请号：US340404

    申请日：1999-06-28

    Applicant: Pei-Wei Tsai ,  Huan-Jen Tseng ,  Chih-Hsien Chang ,  Yi-Hua Chin

    Inventor： Pei-Wei Tsai ,  Huan-Jen Tseng ,  Chih-Hsien Chang ,  Yi-Hua Chin

    IPC: B24B37/04 ,  B24B49/10 ,  B24B57/02 ,  H01L21/00 ,  B24B29/00

    CPC classification number: H01L21/67253 ,  B24B37/04 ,  B24B49/10 ,  B24B57/02

    Abstract: The present invention provides a control device for maintaining a chemical mechanical polishing (CMP) machine in a wet mode, the CMP machine comprising a polishing pad, a slurry sprinkler for sprinkling liquid or deionized water, and at least one carrier head, the control device comprising a sensor positioned on the CMP machine for sensing the operational status of the slurry sprinkler and generating a corresponding sensing signal; and a control unit electrically connected to the sensor for measuring the time period over which the slurry sprinkler is closed wherein when the measured time period exceeds a predetermined length, the control unit will either send a warning signal or turn on the slurry sprinkler to sprinkle liquid onto the polishing pad according to a predetermined process so as to maintain the polishing pad in a wet mode.

    Abstract translation: 本发明提供了一种用于在湿模式下保持化学机械抛光（CMP）机器的控制装置，所述CMP机器包括抛光垫，用于喷洒液体或去离子水的浆料喷洒器，以及至少一个载体头，所述控制装置 包括位于所述CMP机器上的用于感测所述浆料喷洒器的操作状态并产生相应感测信号的传感器; 以及控制单元，电连接到所述传感器，用于测量所述浆料喷洒器关闭的时间段，其中当所测量的时间段超过预定长度时，所述控制单元将发送警告信号或者打开所述浆料喷洒器以喷洒液体 按照预定的处理在抛光垫上，以便将抛光垫保持在湿模式。

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