公开(公告)号：US08519765B2

公开(公告)日：2013-08-27

申请号：US13228508

申请日：2011-09-09

Applicant: Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

Inventor： Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC: H03H11/16

CPC classification number: H03K5/135 ,  H03B19/00 ,  H03L7/099

Abstract: A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.

Abstract translation: 用于信号相位校准的方法包括提供多个周期性时钟信号，包括参考信号和参考信号的多个相移版本。 这些信号具有共同的频率并且相互偏移倍数的相位偏移。 检测到第一信号的边缘。 第一个信号是参考信号的多个相移版本之一。 边缘是从第一逻辑值到第二逻辑值的转换。 第一信号的第二逻辑值在检测到边缘时被比较为除了第一信号之外的第一多个周期性时钟信号之一的第二信号的逻辑值。 基于比较的结果选择性地提供第一信号的反转。

公开(公告)号：US20130038366A1

公开(公告)日：2013-02-14

申请号：US13205722

申请日：2011-08-09

Applicant: Tsung-Hsien TSAI ,  Min-Shueh YUAN ,  Chih-Hsien CHANG

Inventor： Tsung-Hsien TSAI ,  Min-Shueh YUAN ,  Chih-Hsien CHANG

IPC: H03K19/00 ,  H03L7/06

CPC classification number: G01R31/3016 ,  G01R31/31725 ,  G01R31/31726 ,  G01R31/31727 ,  G01R31/3187

Abstract: A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.

Abstract translation: 用于高速应用的BIST电路包括相位差检测电路，具有耦合到相位差检测电路的输出的输入的周期到电流转换电路和耦合到该相位差检测电路的输出的电流 - 电压转换电路 周期到电流转换电路。 相位差检测电路包括用于接收输入时钟信号和输入时钟信号的反相版本的延迟版本作为输入的第一NAND逻辑; 用于接收输入时钟信号的反相版本和输入时钟信号的延迟版本的第二NAND逻辑; 用于接收输入时钟信号和输入时钟信号的延迟版本作为输入的第三NAND逻辑; 以及用于接收输入时钟信号的反相版本和输入时钟信号的反相版本的延迟版本的第四NAND逻辑。

公开(公告)号：US07786771B2

公开(公告)日：2010-08-31

申请号：US12127651

申请日：2008-05-27

Applicant: Tsung-Hsien Tsai ,  Tsung-Yang Hung ,  Chien-Hung Chen ,  Min-Shueh Yuan

Inventor： Tsung-Hsien Tsai ,  Tsung-Yang Hung ,  Chien-Hung Chen ,  Min-Shueh Yuan

IPC: H03L7/06

CPC classification number: H03L7/093 ,  H03L7/0995 ,  H03L7/10 ,  H03L2207/06

Abstract: A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision.

Abstract translation: 提供了具有增益控制的锁相环（PLL）。 PLL具有双路配置，其中响应于PLL输入信号和输出信号之间的相位或频率差产生第一和第二VCO控制电压。 PLL包括动态电压增益控制（DVGC）单元和电压 - 电流（V2I）单元，其中DVGC响应于第一VCO控制电压创建基准参考电流，并且V2I提供基本上线性的电流响应 到第二个VCO控制电压。 来自DVGC和V2I的电流被组合并馈送到电流控制的振荡器中，其产生PLL输出频率信号。 VCO的频率增益显着降低，从而提供具有改进的调谐精度的PLL。

公开(公告)号：US09229050B2

公开(公告)日：2016-01-05

申请号：US13205722

申请日：2011-08-09

Applicant: Tsung-Hsien Tsai ,  Min-Shueh Yuan ,  Chih-Hsien Chang

Inventor： Tsung-Hsien Tsai ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC: G01R31/3187 ,  G01R31/30 ,  G01R31/317

CPC classification number: G01R31/3016 ,  G01R31/31725 ,  G01R31/31726 ,  G01R31/31727 ,  G01R31/3187

Abstract: A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.

Abstract translation: 用于高速应用的BIST电路包括相位差检测电路，具有耦合到相位差检测电路的输出的输入的周期到电流转换电路和耦合到该相位差检测电路的输出的电流 - 电压转换电路 周期到电流转换电路。 相位差检测电路包括用于接收输入时钟信号和输入时钟信号的反相版本的延迟版本作为输入的第一NAND逻辑; 用于接收输入时钟信号的反相版本和输入时钟信号的延迟版本的第二NAND逻辑; 用于接收输入时钟信号和输入时钟信号的延迟版本作为输入的第三NAND逻辑; 以及用于接收输入时钟信号的反相版本和输入时钟信号的反相版本的延迟版本的第四NAND逻辑。

公开(公告)号：US08378654B2

公开(公告)日：2013-02-19

申请号：US12750260

申请日：2010-03-30

Applicant: Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

Inventor： Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

IPC: G05F1/44

CPC classification number: H02M3/158 ,  G05F1/44 ,  G05F1/56

Abstract: A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.

Abstract translation: 提供了具有高精度和电源抑制比（PSRR）的稳压电路。 在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。 电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。 运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。 运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。 运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。 在另一个实施例中，PMOS和NMOS晶体管的作用相反。

公开(公告)号：US20110080220A1

公开(公告)日：2011-04-07

申请号：US12575222

申请日：2009-10-07

Applicant: Tsung-Hsien Tsai ,  Min-Shueh Yuan ,  Chien-Hung Chen

Inventor： Tsung-Hsien Tsai ,  Min-Shueh Yuan ,  Chien-Hung Chen

IPC: H03F1/30

CPC classification number: H03F3/45475 ,  G06G7/18 ,  H03F2200/264 ,  H03F2200/447 ,  H03F2203/45512 ,  H03F2203/45524

Abstract: A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures.

Abstract translation: 代表积分器包括具有输入和输出的放大器; 耦合在所述放大器的输入和输出之间的反馈回路，所述反馈回路包括具有选择用于减小所述积分器的损耗因子的电阻值的补偿电阻器电路; 以及耦合到所述经补偿的电阻器电路的输入端的控制电路，所述控制电路产生用于控制所述经补偿的电阻器电路的控制信号，以基本上维持所选择的用于降低积分器温度范围内的积分器的损耗因子的电阻值。

公开(公告)号：US09148135B2

公开(公告)日：2015-09-29

申请号：US13532881

申请日：2012-06-26

Applicant: Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

Inventor： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC: G06F1/00 ,  H03K5/156 ,  G06F1/08

CPC classification number: H03K5/1565 ,  G06F1/08

Abstract: The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

Abstract translation: 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。

公开(公告)号：US08963649B2

公开(公告)日：2015-02-24

申请号：US13731687

申请日：2012-12-31

Applicant: Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

Inventor： Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC: H03L1/00 ,  H03L7/06 ,  H03B5/10

CPC classification number: H03L1/00 ,  H03B5/10 ,  H03L7/06 ,  H03L7/099 ,  H03L7/0992

Abstract: A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

Abstract translation: 压控振荡器（VCO）包括电流控制振荡器，电压 - 电流转换器和感测电路。 感测电路包括延迟单元，并且感测电路被配置为响应于延迟单元的时间延迟而产生多个补偿控制信号。 电压 - 电流转换器被配置为响应于VCO控制信号和多个补偿控制信号而产生电流信号。 电流控制振荡器被配置为响应于当前信号产生振荡信号。

公开(公告)号：US20130342252A1

公开(公告)日：2013-12-26

申请号：US13532881

申请日：2012-06-26

Applicant: Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

Inventor： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  G06F1/08

Abstract: The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

Abstract translation: 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。

公开(公告)号：US20130127433A1

公开(公告)日：2013-05-23

申请号：US13744037

申请日：2013-01-17

Applicant: Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

Inventor： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

IPC: G05F1/44

CPC classification number: H02M3/158 ,  G05F1/44 ,  G05F1/56

Abstract: A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.

Abstract translation: 一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。 控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。 通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。 响应于输出节点处的电压电平产生反馈信号。 耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。