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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    13.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20160181255A1

    公开(公告)日：2016-06-23

    申请号：US14909135

    申请日：2013-08-06

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Koji NII

    IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  H01L29/78

    CPC classification number: H01L27/1104 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

    Abstract translation: 在图像信息芯片等中，多端口SRAM嵌有逻辑电路。 当使用3端口时，1端口可以用作差分写入和读出端口，并且2端口可以用作单端读出专用端口。 虽然可以减少嵌入式SRAM的占用面积，但是写入和读出端口的数量仅限于一个，并且在单端读出中不能期望读出特性与差分读出一样快。 因此，提供了一种新的布置，其中三个差分写入和读出端口包括在嵌入式SRAM的存储单元结构中，例如N阱区域布置在单元的中心，并且P阱区域 布置在其两侧。

    SEMICONDUCTOR MEMORY DEVICE FOR STABLY READING AND WRITING DATA
    14.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE FOR STABLY READING AND WRITING DATA 有权
    用于稳定读取和写入数据的半导体存储器件

    公开(公告)号：US20160172023A1

    公开(公告)日：2016-06-16

    申请号：US15052188

    申请日：2016-02-24

    Applicant: Renesas Electronics Corporation

    Inventor： Koji NII ,  Shigeki OHBAYASHI ,  Yasumasa TSUKAMOTO ,  Makoto YABUUCHI

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

    Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

    Abstract translation: 在半导体存储器件中，静态存储单元以行和列排列，字线对应于相应的存储单元行，并且字线驱动器对应于字线。 单元电源线对应于相应的存储单元列并且耦合到相应列中的存储器单元的单元电源节点。 向下电源线被布置成对应于相应的存储单元列，保持在数据读取中的接地电压并且在数据写入中被电浮动。 写入辅助元件对应于单电池电源线布置，并且根据写入列指示信号，用于停止向所选列中的单元电源线提供单元电源电压，并且用于耦合布置的单元电源线 对应于所选列至少至相应列上的下电源线。

    Semiconductor Device Having Timing Control For Read-Write Memory Access Operations
    15.
    发明申请
    Semiconductor Device Having Timing Control For Read-Write Memory Access Operations 有权
    具有用于读写存储器访问操作的定时控制的半导体器件

    公开(公告)号：US20150023091A1

    公开(公告)日：2015-01-22

    申请号：US14504994

    申请日：2014-10-02

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii ,  Yoshikazu SAITO ,  Shinji TANAKA ,  Koji NII

    IPC: G11C11/419 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04

    Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

    Abstract translation: 半导体器件避免了干扰问题以及DP-SRAM单元或2P-SRAM单元中的写入和读取操作之间的冲突。 半导体器件1包括写入字线WLA和读取字线WLB，每个读取字线WLB都耦合到存储器单元3.读取操作激活对应于所选择的存储器单元3的读取字线WLB。写入操作激活相应的写入字线WLA 所选择的写入字线WLA在执行读取和写入操作的操作周期中激活所选择的读取字线WLB之后被激活。

    SEMICONDUCTOR DEVICE
    16.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190259443A1

    公开(公告)日：2019-08-22

    申请号：US16287587

    申请日：2019-02-27

    Applicant: Renesas Electronics Corporation

    Inventor： Koji NII

    IPC: G11C11/408 ,  G11C11/16 ,  G11C15/04 ,  G11C7/24 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4097 ,  G11C11/411 ,  G11C11/412

    Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.

    SEMICONDUCTOR DEVICE
    17.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190198107A1

    公开(公告)日：2019-06-27

    申请号：US16192377

    申请日：2018-11-15

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Makoto YABUUCHI ,  Koji NII

    IPC: G11C15/04

    Abstract: A semiconductor device is provided where high-speed search operation can be performed. The semiconductor device includes a plurality of search memory cells arranged in a matrix form a plurality of search line pairs which are respectively provided corresponding to memory cell columns and which respectively transmit a plurality of search data to be compared with data stored in the search memory cells, a plurality of search drivers which are respectively arranged at corresponding to one end sides of the search line pairs and which drive the search line pairs according to the search data, and a plurality of assist circuits which are respectively provided corresponding to the other end sides of the search line pairs and which assist driving corresponding search line pairs according to the search data.

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