公开(公告)号：US09184238B2

公开(公告)日：2015-11-10

申请号：US14270469

申请日：2014-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Hisada ,  Koichi Arai

IPC: H01L29/16 ,  H01L29/808 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/8083 ,  H01L27/098 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66037

Abstract: In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.

Abstract translation: 为了确保杂质扩散率低于硅基的SiC基JFET的性能，确保栅极深度，同时精确地控制栅极区域之间的距离，而不是通过离子注入形成栅极区域到侧壁 的沟渠 这意味着由栅极距离和栅极深度限定的沟道区域应具有高的纵横比。 此外，由于处理的限制，在源极区域内形成栅极区域。 在源极和栅极区域之间形成高度掺杂的PN结导致各种问题，例如结电流的不可避免的增加。 此外，为了形成端接结构，需要显着高能量的离子注入。 在本发明中，提供了一种垂直沟道型SiC功率JFET，其具有位于源极区域之下和栅极区域之下并与源极区分离的浮动栅极区域。

公开(公告)号：US10854588B2

公开(公告)日：2020-12-01

申请号：US15824422

申请日：2017-11-28

Applicant: Renesas Electronics Corporation

Inventor： Hisashi Toyoda ,  Koichi Yamazaki ,  Koichi Arai ,  Tatsuhiro Seki

IPC: H01L25/18 ,  H03K17/10 ,  H03K17/687 ,  H03K17/74 ,  H01L23/00 ,  H01L25/07 ,  H01L29/10 ,  H02P27/06

Abstract: A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off MOSFET having a second gate electrode, a second source electrode and a second drain electrode, and a voltage applying unit which applies a voltage to the first gate electrode. The first source electrode of the junction FET is electrically connected to the second drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series, and the voltage applying unit applies a second voltage with a polarity opposite to that of a first voltage applied to the first gate electrode when the junction FET is brought into an off-state, to the first gate electrode when the MOSFET is in an on-state.

公开(公告)号：US10833188B2

公开(公告)日：2020-11-10

申请号：US16282981

申请日：2019-02-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Hisada ,  Koichi Arai ,  Hironobu Miyamoto

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

公开(公告)号：US10468496B2

公开(公告)日：2019-11-05

申请号：US15790195

申请日：2017-10-23

Applicant: Renesas Electronics Corporation

Inventor： Kenichi Hisada ,  Koichi Arai

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L23/31 ,  H01L29/78 ,  H01L21/04 ,  H01L21/02 ,  H01L23/29 ,  H01L29/739 ,  H01L29/51

Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.

公开(公告)号：US09570602B2

公开(公告)日：2017-02-14

申请号：US15095469

申请日：2016-04-11

Applicant: Renesas Electronics Corporation

Inventor： Koichi Arai ,  Masaki Hama ,  Yasuaki Kagotoshi ,  Kenichi Hisada

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L21/04 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L21/02236 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/049 ,  H01L21/31111 ,  H01L21/32105 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816

Abstract: The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

Abstract translation: 本发明可以通过在湿蚀刻上在衬底上打开绝缘膜来指定在SiC衬底上形成的垂直型功率MOSFET的有源区，提高湿式蚀刻的精度​​和使半导体器件的小型化。 在外延层上依次形成膜厚小的氧化硅膜和膜厚度大于氧化硅膜的多晶硅膜，通过干式蚀刻方法打开多晶硅膜，依次将氧化硅膜为 通过湿蚀刻方法打开，从而暴露有源区中的外延层的上表面。

公开(公告)号：US08835207B2

公开(公告)日：2014-09-16

申请号：US13750615

申请日：2013-01-25

Applicant: Renesas Electronics Corporation

Inventor： Koichi Arai

IPC: H01L21/02 ,  B81C1/00 ,  B81C3/00 ,  H01L29/84 ,  H01L23/48 ,  B81B3/00

CPC classification number: B81B3/0072 ,  B81B3/00 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00896 ,  B81C3/00 ,  B81C2201/056 ,  G01L9/0042 ,  G01L19/06 ,  H01L29/84 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer.

Abstract translation: 在制造在单个半导体芯片上具有MEMS元件的半导体集成电路器件的方法中，MEMS元件的可移动部件在形成重新布线之前被固定。 在重新布线形成之后，晶片被切割。 然后，通过蚀刻晶片来释放MEMS元件的可移动部分。

公开(公告)号：US11631764B2

公开(公告)日：2023-04-18

申请号：US17060486

申请日：2020-10-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Hisada ,  Koichi Arai ,  Hironobu Miyamoto

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

公开(公告)号：US10256339B2

公开(公告)日：2019-04-09

申请号：US16137279

申请日：2018-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasunori Yamashita ,  Koichi Arai ,  Kenichi Hisada

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51

Abstract: In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of apart of the gate insulating film part formed on/over a side face of the trench.

公开(公告)号：US09922829B2

公开(公告)日：2018-03-20

申请号：US15206107

申请日：2016-07-08

Applicant: Renesas Electronics Corporation

Inventor： Koichi Arai ,  Kenichi Hisada

IPC: H01L29/10 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

CPC classification number: H01L21/047 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p−type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n−-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p−-type body layer, and the n−-type drift layer between the p−-type body layer and the n−-type drift layer. By those measures, it is possible to inhibit the operating characteristic from varying.

公开(公告)号：US09543395B2

公开(公告)日：2017-01-10

申请号：US14536625

申请日：2014-11-09

Applicant: Renesas Electronics Corporation

Inventor： Koichi Arai ,  Yasuaki Kagotoshi ,  Nobuo Machida ,  Natsuki Yokoyama ,  Haruka Shimizu

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/36 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66909 ,  H01L29/8083

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract translation: 通常，在诸如基于SiC的正常关断JFET的半导体有源元件中，其中杂质扩散速度显着低于硅中的杂质扩散速度，通过离子注入形成在源区中形成的沟槽的侧壁中形成栅极区。 然而，为了确保JFET的性能，需要高精度地控制栅极区域之间的面积。 此外，存在这样的问题，由于通过在源极区域中形成栅极区域而形成重掺杂的PN结，所以不能避免结电流的增加。 本发明提供一种常闭功率JFET及其制造方法，根据多次外延法形成栅极区域，该方法重复包括外延生长，离子注入和激活退火多次的工艺。