公开(公告)号：US20150364170A1

公开(公告)日：2015-12-17

申请号：US14302727

申请日：2014-06-12

Applicant: QUALCOMM Incorporated

Inventor： Philip Michael Clovis ,  Yi-Hung Tseng ,  Xuhao Huang ,  Sushma Chilukuri

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G06F13/4243 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03L7/07 ,  H03L7/0814

Abstract: A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.

Abstract translation: 提供了一种存储器控制器，其将数据和相应的第一数据选通信号驱动到多个端点。 每个端点被配置为响应于第一数据选通从存储器控制器注册接收到的数据，然后响应于第二数据选通来重新注册接收到的数据。 时钟同步电路用于将所接收的第一数据选通信号保持在其中一个端点与第二数据选通脉冲充分同步。

公开(公告)号：US20150340078A1

公开(公告)日：2015-11-26

申请号：US14816820

申请日：2015-08-03

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC: G11C11/4076 ,  H03L7/093

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

Abstract translation: 根据某些实施例提供了用于数据同步的方法。 该方法包括接收数据，数据时钟信号和清洁时钟信号，使用数据时钟信号对数据进行采样，使采样数据与干净的时钟信号同步，并输出同步的采样数据。 该方法还包括跟踪数据时钟信号和干净的时钟信号之间的相位漂移，以及如果跟踪的相位漂移在第一个时钟信号中达到第一个值，则将干扰时钟信号的同步采样数据的输出拉入一个时钟周期 方向。

公开(公告)号：US20140266103A1

公开(公告)日：2014-09-18

申请号：US13843121

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Yuhe Wang ,  Marzio Pedrali-Noy ,  Xuhao Huang ,  Martin Saint-Laurent ,  Xufeng Chen

IPC: G05F1/46

CPC classification number: G05F1/462 ,  G05F1/565 ,  G05F1/575

Abstract: Techniques are described that embed a digital assisted regulator with an LDO regulator on a chip without requiring a capacitor external to the chip and to regulate a voltage without undershoot. The digital assisted regulator responds to information regarding operation of the LDO regulator and to a signal that provides advance notification of a load change. When the advance notification signal is received, the digital assisted regulator pulls a circuit's supply voltage up to a chip's incoming supply voltage. When the correct operating voltage has been reached and any undershoot problem removed, the digital assisted regulator balances the current it provides with the current provided by the LDO regulator, to allow a quick response time for other load changes. Also, bandwidth of an LDO regulator may be expanded by use of an advance notice signal to increase bias current of an LDO output device to meet an upcoming load change.

Abstract translation: 描述了将芯片上的LDO调节器嵌入数字辅助调节器的技术，而不需要芯片外部的电容器并且调节电压而不会下冲。 数字辅助稳压器响应关于LDO调节器的操作的信息以及提供负载变化的提前通知的信号。 当接收到提前通知信号时，数字辅助调节器将电路的电源电压提升到芯片的输入电源电压。 当达到正确的工作电压并消除任何下冲问题时，数字辅助调节器将其提供的电流与LDO调节器提供的电流平衡，以允许其他负载变化的快速响应时间。 此外，LDO调节器的带宽可以通过使用提前通知信号来扩展，以增加LDO输出设备的偏置电流以满足即将到来的负载变化。

公开(公告)号：US12101089B2

公开(公告)日：2024-09-24

申请号：US17970519

申请日：2022-10-20

Applicant: QUALCOMM Incorporated

Inventor： Xu Zhang ,  Xuhao Huang

IPC: H03K19/01 ,  H03K3/037 ,  H03K19/0185 ,  H04M1/02

CPC classification number: H03K19/018521 ,  H03K3/037 ,  H04M1/026

Abstract: A level-shifter is provided with a first transistor and a second transistor. The first transistor functions to discharge an internal node responsive to an assertion of an inverted input signal to a first power supply voltage. A second transistor functions to discharge an inverted level-shifter output signal responsive to an assertion of an input signal to the first power supply voltage. An inverter inverts the inverted level-shifter output signal to form a level-shifter output signal that is asserted to a second power supply voltage responsive to the assertion of the input signal.

公开(公告)号：US10013010B1

公开(公告)日：2018-07-03

申请号：US15398825

申请日：2017-01-05

Applicant: QUALCOMM Incorporated

Inventor： Sungmin Ock ,  Xuhao Huang

IPC: G05F1/575

Abstract: A voltage droop reduction circuit generally including a loop coupled to an output of a voltage regulator is provided. The loop includes a first current amplifier. The voltage droop reduction circuit may also include a first capacitor coupled between the output of the voltage regulator and an input of the first current amplifier.

公开(公告)号：US10003328B1

公开(公告)日：2018-06-19

申请号：US15680120

申请日：2017-08-17

Applicant: QUALCOMM Incorporated

Inventor： Wenjing Yin ,  Xuhao Huang

IPC: H03K3/017 ,  H03K7/08 ,  H03K5/156 ,  H03K5/05 ,  H03K5/135

CPC classification number: H03K5/156 ,  H03K3/017 ,  H03K3/02315 ,  H03K4/501 ,  H03K5/05 ,  H03K5/135 ,  H03K7/08

Abstract: A hybrid pulse-width control circuit is provided that includes a ramp voltage generator for generating a ramp voltage signal. A clock pulse generator asserts an output clock signal responsive to the ramp voltage signal equaling a reference voltage.

公开(公告)号：US09602433B2

公开(公告)日：2017-03-21

申请号：US13841355

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Xuhao Huang ,  Ankit Srivastava ,  Xiaohong Quan ,  Seyfollah S Bazarjani

IPC: H04L12/28 ,  H04L12/947 ,  H04L12/40 ,  H04L12/403 ,  H04L25/02

CPC classification number: H04L49/25 ,  H04L12/40006 ,  H04L12/4035 ,  H04L25/0272

Abstract: An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.

公开(公告)号：US09478268B2

公开(公告)日：2016-10-25

申请号：US14302727

申请日：2014-06-12

Applicant: QUALCOMM Incorporated

Inventor： Philip Michael Clovis ,  Yi-Hung Tseng ,  Xuhao Huang ,  Sushma Chilukuri

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/42 ,  G06F13/16 ,  G11C29/02 ,  H03L7/081 ,  H03L7/07

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G06F13/4243 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03L7/07 ,  H03L7/0814

Abstract: A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.

Abstract translation: 提供了一种存储器控制器，其将数据和相应的第一数据选通信号驱动到多个端点。 每个端点被配置为响应于第一数据选通从存储器控制器注册接收到的数据，然后响应于第二数据选通来重新注册接收到的数据。 时钟同步电路用于将所接收的第一数据选通信号保持在其中一个端点与第二数据选通脉冲充分同步。

公开(公告)号：US09191193B1

公开(公告)日：2015-11-17

申请号：US14335185

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： Xuhao Huang ,  Yi-Hung Tseng ,  Philip Michael Clovis ,  Sushma Chilukuri

IPC: H03D3/24 ,  H04L7/033 ,  H03L7/081

CPC classification number: H03L7/10 ,  H03L7/0812 ,  H03L7/0814

Abstract: A clock synchronization circuit includes a multi-phase clock generator to generate a plurality of delayed clocks, each delayed clock having a unique delay with regard to a source clock. The clock synchronization circuit further includes a selection circuit that selects one of the delayed clocks according to a phase error to form a local clock driven into a local clock path and received at the clock synchronization circuit as a received local clock. The selection circuit determines the phase error by comparing the received local clock to a reference clock.

Abstract translation: 时钟同步电路包括产生多个延迟时钟的多相时钟发生器，每个延迟时钟具有关于源时钟的唯一延迟。 时钟同步电路还包括选择电路，其根据相位误差选择延迟时钟之一，以形成被驱动到本地时钟路径中并在时钟同步电路处接收的本地时钟作为接收到的本地时钟。 选择电路通过将接收到的本地时钟与参考时钟进行比较来确定相位误差。

公开(公告)号：US09123408B2

公开(公告)日：2015-09-01

申请号：US13902705

申请日：2013-05-24

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract translation: 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。