公开(公告)号：US20140347941A1

公开(公告)日：2014-11-27

申请号：US13902705

申请日：2013-05-24

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC分类号： G11C7/22

CPC分类号： G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

摘要： In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

摘要翻译： 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。

公开(公告)号：US11467621B2

公开(公告)日：2022-10-11

申请号：US16804045

申请日：2020-02-28

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Ravi Jenkal ,  Donghyun Kim

IPC分类号： G06F1/08 ,  G06F9/48 ,  G06F9/38 ,  G06F1/3206

摘要： Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

公开(公告)号：US09437278B2

公开(公告)日：2016-09-06

申请号：US14816820

申请日：2015-08-03

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Vijayalakshmi Sriramagiri ,  Marzio Pedrali-Noy

IPC分类号： G11C11/4076 ,  H03L7/093 ,  G11C7/22 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093

CPC分类号： G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

摘要： A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

摘要翻译： 根据某些实施例提供了用于数据同步的方法。 该方法包括接收数据，数据时钟信号和清洁时钟信号，使用数据时钟信号对数据进行采样，使采样数据与干净的时钟信号同步，并输出同步的采样数据。 该方法还包括跟踪数据时钟信号和干净的时钟信号之间的相位漂移，以及如果跟踪的相位漂移在第一个时钟信号中达到第一个值，则将干扰时钟信号的同步采样数据的输出拉入一个时钟周期 方向。

公开(公告)号：US20210271287A1

公开(公告)日：2021-09-02

申请号：US16804045

申请日：2020-02-28

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Ravi Jenkal ,  Donghyun Kim

IPC分类号： G06F1/08 ,  G06F9/48 ,  G06F1/3206 ,  G06F9/38

摘要： Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

公开(公告)号：US09875785B2

公开(公告)日：2018-01-23

申请号：US15246371

申请日：2016-08-24

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Michael Drop

IPC分类号： G11C11/4076 ,  G11C11/406 ,  G11C11/408

CPC分类号： G11C11/40615 ,  G06F13/1636 ,  G11C11/40611 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2211/4067

摘要： A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

公开(公告)号：US20150340078A1

公开(公告)日：2015-11-26

申请号：US14816820

申请日：2015-08-03

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC分类号： G11C11/4076 ,  H03L7/093

CPC分类号： G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

摘要： A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

摘要翻译： 根据某些实施例提供了用于数据同步的方法。 该方法包括接收数据，数据时钟信号和清洁时钟信号，使用数据时钟信号对数据进行采样，使采样数据与干净的时钟信号同步，并输出同步的采样数据。 该方法还包括跟踪数据时钟信号和干净的时钟信号之间的相位漂移，以及如果跟踪的相位漂移在第一个时钟信号中达到第一个值，则将干扰时钟信号的同步采样数据的输出拉入一个时钟周期 方向。

公开(公告)号：US20170098470A1

公开(公告)日：2017-04-06

申请号：US15246371

申请日：2016-08-24

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Michael Drop

IPC分类号： G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC分类号： G11C11/40615 ,  G06F13/1636 ,  G11C11/40611 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2211/4067

摘要： A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

公开(公告)号：US09123408B2

公开(公告)日：2015-09-01

申请号：US13902705

申请日：2013-05-24

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC分类号： G11C7/22 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093

CPC分类号： G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

摘要： In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

摘要翻译： 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。

公开(公告)号：US12099378B2

公开(公告)日：2024-09-24

申请号：US17963129

申请日：2022-10-10

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Ravi Jenkal ,  Donghyun Kim

IPC分类号： G06F1/08 ,  G06F1/3206 ,  G06F9/38 ,  G06F9/48

CPC分类号： G06F1/08 ,  G06F1/3206 ,  G06F9/3877 ,  G06F9/4837 ,  G06F9/4843

摘要： Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

公开(公告)号：US20230118950A1

公开(公告)日：2023-04-20

申请号：US17963129

申请日：2022-10-10

申请人： QUALCOMM Incorporated

发明人： Edwin Jose ,  Ravi Jenkal ,  Donghyun Kim

IPC分类号： G06F1/08 ,  G06F9/48 ,  G06F9/38 ,  G06F1/3206

摘要： Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.