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公开(公告)号：US12130648B2
公开(公告)日：2024-10-29
申请号：US18302734
申请日：2023-04-18
发明人： Marko Koski , Edgar Marti-Arbona , Gordon Lee , Anish Muttreja , Ravi Jenkal
CPC分类号： G05F1/5735 , G05F1/562 , H02M1/0009 , H02M1/0025
摘要： A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.
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公开(公告)号：US20210294369A1
公开(公告)日：2021-09-23
申请号：US17207478
申请日：2021-03-19
发明人： Marko KOSKI , Edgar Marti-Arbona , Gordon Lee , Anish Muttreja , Ravi Jenkal
摘要： A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.
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公开(公告)号：US20210271287A1
公开(公告)日：2021-09-02
申请号：US16804045
申请日：2020-02-28
发明人： Edwin Jose , Ravi Jenkal , Donghyun Kim
IPC分类号： G06F1/08 , G06F9/48 , G06F1/3206 , G06F9/38
摘要： Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.
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公开(公告)号：US20190332138A1
公开(公告)日：2019-10-31
申请号：US15967456
申请日：2018-04-30
发明人： Kevin Bowles , Anish Muttreja , Ravi Jenkal
摘要： A system is provided that controls the clocking of a processor depending upon its usage of execution units. As the processor transitions from a default mode of operation using a default number of the execution units to an increased load mode of operation using an increased number of the execution units, a current drawn by the processor from a power rail remains substantially unchanged.
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公开(公告)号：US11662757B2
公开(公告)日：2023-05-30
申请号：US17207478
申请日：2021-03-19
发明人： Marko Koski , Edgar Marti-Arbona , Gordon Lee , Anish Muttreja , Ravi Jenkal
CPC分类号： G05F1/5735 , G05F1/562 , H02M1/0009 , H02M1/0025
摘要： A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.
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公开(公告)号：US11467621B2
公开(公告)日：2022-10-11
申请号：US16804045
申请日：2020-02-28
发明人： Edwin Jose , Ravi Jenkal , Donghyun Kim
IPC分类号： G06F1/08 , G06F9/48 , G06F9/38 , G06F1/3206
摘要： Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.
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公开(公告)号：US12099397B2
公开(公告)日：2024-09-24
申请号：US18069537
申请日：2022-12-21
发明人： Prashanth Kumar Kakkireni , Matthew Severson , Ravi Jenkal , Gordon Lee , Kevin Bradley Citterelle , Ronald Alton , Anish Muttreja
IPC分类号： G06F1/32 , G06F1/3296
CPC分类号： G06F1/3296
摘要： Various embodiments include power management system methods including receiving, at a processor(s), a notification signal triggering the processor(s) to implement power usage mitigation at the processor(s), determining, by the processor(s), a mitigation amount of power rail power by which to mitigate current usage at a power rail based on a use case for the power rail, and implementing power usage mitigation at the processor(s) by the processor(s) sufficient to mitigate power usage at the power rail by the mitigation amount of power rail power. Power usage mitigation may include reducing processor(s) current usage: by a predefined amount; proportional to the amount a power rail current exceeds a power rail current threshold; by the amount of current exceeding a processor current threshold; or by a smallest amount between the amount a power rail current exceeds a power rail current threshold and the processor(s) current exceeds a processor current threshold.
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公开(公告)号：US12099378B2
公开(公告)日：2024-09-24
申请号：US17963129
申请日：2022-10-10
发明人： Edwin Jose , Ravi Jenkal , Donghyun Kim
IPC分类号： G06F1/08 , G06F1/3206 , G06F9/38 , G06F9/48
CPC分类号： G06F1/08 , G06F1/3206 , G06F9/3877 , G06F9/4837 , G06F9/4843
摘要： Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.
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公开(公告)号：US20230118950A1
公开(公告)日：2023-04-20
申请号：US17963129
申请日：2022-10-10
发明人： Edwin Jose , Ravi Jenkal , Donghyun Kim
IPC分类号： G06F1/08 , G06F9/48 , G06F9/38 , G06F1/3206
摘要： Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.
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公开(公告)号：US10606305B2
公开(公告)日：2020-03-31
申请号：US15967456
申请日：2018-04-30
发明人： Kevin Bowles , Anish Muttreja , Ravi Jenkal
摘要： A system is provided that controls the clocking of a processor depending upon its usage of execution units. As the processor transitions from a default mode of operation using a default number of the execution units to an increased load mode of operation using an increased number of the execution units, a current drawn by the processor from a power rail remains substantially unchanged.
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