公开(公告)号：US09660110B2

公开(公告)日：2017-05-23

申请号：US14498359

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Sang-June Park ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  David Francis Berdy ,  Matthew Michael Nowak ,  Robert Paul Mikulka

IPC: H01L29/93 ,  H01L29/94 ,  H01L27/06

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/94

Abstract: An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.

公开(公告)号：US20170141756A1

公开(公告)日：2017-05-18

申请号：US15137662

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy ,  Yunfei Ma ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H03H9/54 ,  H03H3/02 ,  H03H3/08 ,  H03H9/64

CPC classification number: H03H9/542 ,  H01F17/0013 ,  H01F2017/002 ,  H01F2017/0026 ,  H03H3/02 ,  H03H3/08 ,  H03H7/0123 ,  H03H7/461 ,  H03H9/0547 ,  H03H9/0557 ,  H03H9/0561 ,  H03H9/1014 ,  H03H9/1071 ,  H03H9/64 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/0014 ,  H05K3/4602

Abstract: A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.

公开(公告)号：US20170133996A1

公开(公告)日：2017-05-11

申请号：US14936998

申请日：2015-11-10

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Chengjie Zuo ,  David Francis Berdy ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H03H7/01 ,  H03H3/00 ,  H01L23/66 ,  H01L49/02 ,  H01L25/18

CPC classification number: H03H7/0115 ,  H01L23/66 ,  H01L25/0657 ,  H01L25/18 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6677 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2225/06513 ,  H01L2225/06541 ,  H03H7/1766 ,  H03H7/1775

Abstract: A circuit includes a localized metal-insulator-metal (MIM) capacitor array in a radio frequency (RF) front end circuit, which is integrated on a first die, and includes a localized common shared ground node within the localized MIM capacitor array, a plurality of inductors, and a plurality of RF filters. Each of the plurality of RF filters includes a plurality of passive resonant frequency circuits, and each of the plurality of passive resonant frequency circuits is implemented utilizing one or more MIM capacitors in the localized MIM capacitor array, and one or more of the plurality of inductors. The plurality of inductors may be arranged at a periphery of the localized MIM capacitor array on the first die or integrated on a second die, which is coupled to the first die. Each of the MIM capacitors in the localized MIM capacitor array has a different capacitance value.

公开(公告)号：US20170084531A1

公开(公告)日：2017-03-23

申请号：US14861958

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L23/498 ,  H01L21/8234 ,  H01L21/306 ,  H01L27/088 ,  H01L27/12 ,  H01L23/66 ,  H01L21/84 ,  H01L21/304

CPC classification number: H01L27/1203 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/66 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L29/1087 ,  H01L29/66772

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

公开(公告)号：US20170077079A1

公开(公告)日：2017-03-16

申请号：US14853701

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey Lan ,  Niranjan Sunil Mudakatte ,  Changhan Hobie Yun ,  Daeik Daniel Kim ,  Chengjie Zuo ,  David Francis Berdy ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L27/01 ,  H01L49/02

CPC classification number: H01L27/01 ,  H01L21/4846 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L28/10 ,  H01L28/75 ,  H01L2224/11

Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.

Abstract translation: 一种装置包括玻璃基板和电容器。 电容器包括耦合到第一电极的第一金属，电介质结构和包括电容器的第二电极的通孔结构。 第一金属结构通过电介质结构与通孔结构分离。

公开(公告)号：US20160181233A1

公开(公告)日：2016-06-23

申请号：US14580900

申请日：2014-12-23

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Daeik Daniel Kim ,  David Francis Berdy ,  Chengjie Zuo ,  Jonghae Kim ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Robert Paul Mikulka

IPC: H01L27/01 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01G4/33 ,  H01G4/38 ,  H01L27/016 ,  H01L27/0805 ,  H01L2224/18

Abstract: Metal-insulator-metal (MIM) capacitors arranged in a pattern to reduce inductance, and related methods, are disclosed. In one aspect, circuits are provided that employ MIM capacitors coupled in series. The MIM capacitors are arranged in a pattern, wherein a MIM capacitor is placed so as to be electromagnetically adjacent to at least two MIM capacitors, and so that a current of the MIM capacitor flows in a direction opposite or substantially opposite of a direction in which a current of each adjacent MIM capacitor flows. The magnetic field generated at metal connections of each MIM capacitor rotates in an opposite direction of the magnetic field of each electromagnetically adjacent MIM capacitor, and thus a larger proportion of magnetic fields cancel out one another rather than combining, reducing equivalent series inductance (ESL) compared to linear arrangement of MIMs.

Abstract translation: 公开了以图案排列以降低电感的金属绝缘体金属（MIM）电容器及相关方法。 在一个方面，提供了采用串联耦合的MIM电容器的电路。 MIM电容器以图案布置，其中MIM电容器放置成与至少两个MIM电容器电磁相邻，并且使得MIM电容器的电流沿与其中的MIM方向相反或基本上相反的方向流动 每个相邻MIM电容器的电流流动。 在每个MIM电容器的金属连接处产生的磁场沿与每个电磁相邻的MIM电容器的磁场相反的方向旋转，因此较大比例的磁场彼此抵消而不是组合，从而减小了等效串联电感（ESL） 与MIM的线性排列相比。

公开(公告)号：US10319694B2

公开(公告)日：2019-06-11

申请号：US15233902

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik Kim ,  Jie Fu ,  Manuel Aldrete ,  Jonghae Kim ,  Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Mario Francisco Velez

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.

公开(公告)号：US10154591B2

公开(公告)日：2018-12-11

申请号：US15896959

申请日：2018-02-14

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H05K5/00 ,  H05K1/18 ,  H03H7/01 ,  H05K3/10 ,  H05K3/30 ,  H05K3/40 ,  H05K1/02 ,  H05K1/14 ,  H01L21/56 ,  H01L23/12 ,  H01L23/15 ,  H01L23/28 ,  H01L23/538 ,  H01L23/552

Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.

公开(公告)号：US10141353B2

公开(公告)日：2018-11-27

申请号：US15161152

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Daeik Daniel Kim ,  Jonghae Kim ,  Mario Francisco Velez ,  Chengjie Zuo ,  David Francis Berdy

IPC: H01L27/13 ,  H03H7/01 ,  H01L21/84 ,  H01L49/02 ,  H01L23/498 ,  H03H1/00

Abstract: The present disclosure provides integrated circuit apparatuses and methods for manufacturing integrated circuit apparatuses. An integrated circuit apparatus may include a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface, a first conductor disposed on the first insulator, a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface, a second conductor disposed on the second insulator, and a dielectric layer disposed between the first bottom conductor of the first insulator and the second top conductor of the second insulator.

公开(公告)号：US10103703B2

公开(公告)日：2018-10-16

申请号：US15161138

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Jonghae Kim ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka

IPC: H03H7/01 ,  H01F5/00 ,  H01F41/04 ,  H01P1/203 ,  H03H7/09 ,  H05K1/18 ,  H03H1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/18 ,  H05K3/40 ,  H01P1/213 ,  H01P5/12 ,  H03H7/46

Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.