公开(公告)号：US09489305B2

公开(公告)日：2016-11-08

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： George Patsilaras ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Kris Tiri ,  Jeong-Ho Woo ,  Anwar Rohillah ,  Feng Wang ,  Moinul Khan ,  Subbarao Palacharla

IPC: G06F12/00 ,  G06F12/08 ,  G06F1/32 ,  G06F13/16 ,  G06F9/46

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。

公开(公告)号：US20180329465A1

公开(公告)日：2018-11-15

申请号：US15592664

申请日：2017-05-11

Applicant: QUALCOMM INCORPORATED

Inventor： MEHRAD TAVAKOLI ,  Idreas Mir ,  Moinul Khan ,  Ronald Alton ,  Gheorghe Cascaval ,  Rajiv Vijayakumar ,  Mriganka Mondal ,  Maurice Ribble ,  Martin Renschler

IPC: G06F1/20 ,  G06F1/32 ,  G06F1/26 ,  G06F11/34

CPC classification number: G06F1/206 ,  G06F1/163 ,  G06F1/266 ,  G06F1/3215 ,  G06F1/3218 ,  G06F1/3234 ,  G06F3/012 ,  G06F11/3495

Abstract: Disclosed are methods and systems for intelligent adjustment of an immersive multimedia workload in a portable computing device (“PCD”), such as a virtual reality (“VR”) or augmented reality (“AR”) workload. An exemplary embodiment monitors one or more performance indicators comprising a motion to photon latency associated with the immersive multimedia workload. Performance parameters associated with thermally aggressive processing components are adjusted to reduce demand for power while ensuring that the motion to photon latency is and/or remains optimized. Performance parameters that may be adjusted include, but are not limited to including, eye buffer resolution, eye buffer MSAA, timewarp CAC, eye buffer FPS, display FPS, timewarp output resolution, textures LOD, 6DOF camera FPS, and fovea size.

公开(公告)号：US09779471B2

公开(公告)日：2017-10-03

申请号：US14504047

申请日：2014-10-01

Applicant: QUALCOMM Incorporated

Inventor： Sudeep Ravi Kottilingal ,  Moinul Khan ,  Colin Christopher Sharp

IPC: G06T1/60 ,  G06F12/109 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/657 ,  G06T1/20 ,  G06T2200/28

Abstract: A transparent format converter (TFC) may determine that a request by at least one processor for graphics data stored in graphics memory is indicative of a request for graphics data in a first data format. The TFC may retrieve the graphics data in a second data format from the graphics memory based at least in part on the request for the graphics data in the graphics memory. The TFC may convert the retrieved graphics data from the second data format to the first data format. The TFC may store the converted graphics data in the first data format into a memory that is accessible by the at least one processor.

公开(公告)号：US09690710B2

公开(公告)日：2017-06-27

申请号：US14598049

申请日：2015-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Feng Wang ,  Bohuslav Rychlik ,  Moinul Khan

IPC: G06F12/00 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0868

CPC classification number: G06F12/0888 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0835 ,  G06F12/0868 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/62 ,  Y02D10/13

Abstract: Systems and methods for improved operation of a victim cache in a portable computing device (PCD) are presented. A lower level cache is operated as a victim to an upper level cache, the lower level cache containing a plurality of cache lines. A filter is operated in association with the lower level victim cache, and reflects the cache lines contained in the victim cache. For a miss at the upper level cache, the filter is checked to determine if the requested cache line is in the victim cache. If checking the filter determines that the requested cache line is in the victim cache the requested cache line is retrieved from the victim cache. If checking the filter determines that the request cache line is not in the victim cache, the victim cache is bypassed and the cache line is requested from a memory controller.

公开(公告)号：US09632562B2

公开(公告)日：2017-04-25

申请号：US14616720

申请日：2015-02-08

Applicant: QUALCOMM INCORPORATED

Inventor： Nhon Toai Quach ,  Virat Deepak ,  Oscar Cabral Arias ,  Yanru Li ,  Haw-Jing Lo ,  Michael Drop ,  Venkata Narayana Ramesh Pinnamaraju Durga ,  Moinul Khan

IPC: G06F1/32 ,  G11C11/4074 ,  G11C11/409 ,  H03M7/30

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/401 ,  G11C11/4074 ,  G11C11/409 ,  H03M7/30 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

公开(公告)号：US09612970B2

公开(公告)日：2017-04-04

申请号：US14333981

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Pankaj Chaurasia ,  Raghu Sankuratri

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/084 ,  G06F12/12 ,  G06F12/10 ,  G06F12/0895

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

公开(公告)号：US09558117B2

公开(公告)日：2017-01-31

申请号：US14597992

申请日：2015-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Feng Wang ,  Bohuslav Rychlik ,  Moinul Khan

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0848 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/282 ,  G06F2212/283 ,  G06F2212/6012 ,  G06F2212/604

Abstract: Systems and methods for adaptive implementation of victim cache modes in a portable computing device (PCD) are presented. In operation, an upper level cache is partitioned into a main portion and a sample portion; and a lower level cache is partitioned into a corresponding main portion and sample portion in communication with the main portion and sample portion of the upper level cache. A victim mode sample data set and a normal mode sample data set are obtained from the lower level cache. Based on the victim mode and a normal mode sample data sets, a determination is made whether to operate the lower level cache as a victim to the upper level cache. The main portion of lower level cache is caused to operate either as a victim or non-victim to the main portion of the upper level cache in accordance with the determination.

Abstract translation: 提出了在便携式计算设备（PCD）中自适应实现受害者缓存模式的系统和方法。 在操作中，上级缓存被分割成主要部分和样本部分; 并且下级缓存被分割成与上级高速缓存的主要部分和采样部分通信的对应主要部分和采样部分。 从下级缓存获得受害者模式样本数据集和正常模式样本数据集。 基于受害者模式和正常模式的采样数据集，确定是否将较低级别的高速缓存操作为上级缓存的受害者。 下级缓存的主要部分根据该确定被作为高级缓存的主要部分作为受害者或不受害者操作。

公开(公告)号：US20150234761A1

公开(公告)日：2015-08-20

申请号：US14706203

申请日：2015-05-07

Applicant: QUALCOMM Incorporated

Inventor： Cristian Duroiu ,  Jaya Prakash Subramaniam Ganasan ,  Vinod Chamarty ,  Mark Michael Schaffer ,  Joshua Hirsch Stubbs ,  Robert Nicholson Gibson ,  Kris Tiri ,  Moinul Khan ,  Bohuslav Rychlik ,  Serag GadelRab ,  Simon Booth

IPC: G06F13/37 ,  G06F13/16 ,  G06F13/18 ,  G06F13/42

CPC classification number: G06F13/37 ,  G06F13/1626 ,  G06F13/18 ,  G06F13/362 ,  G06F13/4256 ,  G06F2213/0038 ,  G06F2213/0062 ,  G06F2213/0064 ,  G06F2213/36 ,  Y02D10/14

Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Abstract translation: 公开了用于基于健康信息在通信总线上仲裁总线事务的设备，系统，方法和计算机可读介质。 主设备的健康信息可用于调整主设备总线事务的优先级，以满足主设备的服务质量要求。 在一个实施例中，总线互连被提供和配置为将总线事务从多个主设备中的任一个传送到耦合总线互连的从设备。 总线互连还被配置为将多个主设备中的每一个的健康信息映射到虚拟优先级空间中。 总线互连还被配置为将虚拟优先级空间转换为多个主设备中的每一个的物理优先级。 总线互连还被配置为基于多个主设备的物理优先级来仲裁多个主设备的总线事务。

公开(公告)号：US20200066024A1

公开(公告)日：2020-02-27

申请号：US16674669

申请日：2019-11-05

Applicant: QUALCOMM Incorporated

Inventor： Mehrad Tavakoli ,  Moinul Khan ,  Martin Renschler ,  Mriganka Mondal

IPC: G06T15/00 ,  G06F3/01 ,  G06T3/00 ,  G06K9/00

Abstract: An apparatus is configured to render graphics content to reduce latency of the graphics content. The apparatus includes a display configured to present graphics content including a first portion corresponding to an area of interest and further including a second portion. The apparatus further includes a fovea estimation engine configured to generate an indication of the area of interest based on scene information related to the graphics content. The apparatus further includes a rendering engine responsive to the fovea estimation engine. The rendering engine is configured to perform a comparison of a first result of an evaluation metric on part of the area of interest with a second result of the evaluation metric with another part of the area of interest. The rendering engine is further configured to render the graphics content using predictive adjustment to reduce latency based on the comparison.

公开(公告)号：US10484685B2

公开(公告)日：2019-11-19

申请号：US15490625

申请日：2017-04-18

Applicant: QUALCOMM INCORPORATED

Inventor： Serag Gadelrab ,  Chinchuan Chiu ,  Moinul Khan ,  Kyle Ernewein ,  Tom Longo ,  Simon Booth ,  Meghal Varia ,  Milivoje Aleksic ,  King-Chung Lai

IPC: H04N19/127 ,  G06F3/06 ,  H04N19/426 ,  H04N19/176 ,  H04N19/65 ,  G06T3/40 ,  G01K13/00

Abstract: An exemplary method for intelligent compression defines a threshold value for a key performance indicator. Based on the key performance indicator value, data blocks generated by a producer component may be scaled down to reduce power and/or bandwidth consumption when being compressed according to a lossless compression module. The compressed data blocks are then stored in a memory component along with metadata that signals the scaling factor used prior to compression. Consumer components later retrieving the compressed data blocks from the memory component may decompress the data blocks and upscale, if required, based on the scaling factor signaled by the metadata.