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    SYNCHRONIZATION OF ENDPOINTS USING TUNABLE LATENCY
    1.
    发明申请
    SYNCHRONIZATION OF ENDPOINTS USING TUNABLE LATENCY 有权

    公开(公告)号：US20170085331A1

    公开(公告)日：2017-03-23

    申请号：US14858437

    申请日：2015-09-18

    Applicant: QUALCOMM Incorporated

    Inventor： Phillip Michael Clovis ,  Michael Drop ,  Isaac Berk

    IPC: H04J3/06 ,  H04L7/033

    CPC classification number: H04J3/0658 ,  G06F13/1689 ,  G06F13/4291 ,  H04L7/0331

    Abstract: A memory controller is provided to increment a source timestamp count responsive to a clock signal. Further, the memory controller associates the source timestamp count to a respective word for each endpoint in a plurality of endpoints. The memory controller transmits the received clock signal, a respective data word, and an associated source count to each endpoint. Each endpoint increments a destination count responsive to the clock signal. Each endpoint further transmits its respective word to an external memory responsive to the destination count being greater than or equal to the associated source count by a threshold margin.

    DYNAMIC RANDOM ACCESS MEMORY TIMING ADJUSTMENTS
    2.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY TIMING ADJUSTMENTS 审中-公开
    动态随机存取时间调整

    公开(公告)号：US20160093345A1

    公开(公告)日：2016-03-31

    申请号：US14497902

    申请日：2014-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Dexter Tamio Chun ,  Michael Drop ,  Raghu Sankuratri

    IPC: G11C7/10

    CPC classification number: G11C7/1072 ,  G06F13/1689

    Abstract: A method includes detecting, at a controller, a rate-of-change between first data traffic to be sent to a dynamic random access memory (DRAM) at a first time and second data traffic to be sent to the DRAM at a second time. The method also includes adjusting a data rate of the second data traffic in response to a determination that the rate-of-change satisfies a threshold.

    Abstract translation: 一种方法包括在控制器处检测要发送到第一时间的动态随机存取存储器（DRAM）的第一数据业务和第二时间发送到DRAM的第二数据业务之间的变化率。 该方法还包括响应于变化率满足阈值的确定来调整第二数据业务的数据速率。

    LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM
    6.
    发明申请
    LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM 有权
    用于MESOCHRONOUS DDR系统的低延迟同步方案

    公开(公告)号：US20150340078A1

    公开(公告)日：2015-11-26

    申请号：US14816820

    申请日：2015-08-03

    Applicant: QUALCOMM Incorporated

    Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

    IPC: G11C11/4076 ,  H03L7/093

    CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

    Abstract: A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

    Abstract translation: 根据某些实施例提供了用于数据同步的方法。 该方法包括接收数据，数据时钟信号和清洁时钟信号，使用数据时钟信号对数据进行采样，使采样数据与干净的时钟信号同步，并输出同步的采样数据。 该方法还包括跟踪数据时钟信号和干净的时钟信号之间的相位漂移，以及如果跟踪的相位漂移在第一个时钟信号中达到第一个值，则将干扰时钟信号的同步采样数据的输出拉入一个时钟周期 方向。

    METHOD AND APPARATUS FOR DRAM SPATIAL COALESCING WITHIN A SINGLE CHANNEL
    7.
    发明申请
    METHOD AND APPARATUS FOR DRAM SPATIAL COALESCING WITHIN A SINGLE CHANNEL 有权
    用于单个通道中的DRAM空间分析的方法和装置

    公开(公告)号：US20150186267A1

    公开(公告)日：2015-07-02

    申请号：US14142573

    申请日：2013-12-27

    Applicant: QUALCOMM Incorporated

    Inventor： Dexter Tamio Chun ,  Haw-Jing Lo ,  Michael Drop

    IPC: G06F12/06

    CPC classification number: G06F12/06 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1673 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

    Abstract translation: 方面包括用于重新组织存储器中的数据存储器的计算设备，系统和方法，以激励小于用于读取或写入事务的存储器模块的所有存储器设备。 存储器件可以连接到单独的选择线，使得重新排序逻辑可以根据重新排序的存储器映射来确定存储器件激活事务。 重新排序逻辑可以重新排序存储器地址，使得由处理器为交易提供的存储器地址根据重新排序的存储器映射被转换为重新排序的存储器地址，而处理器不必改变其存储器地址方案。 重新排序的存储器映射可以提供由存储器件减少的能量消耗，或等待容忍过程的能量消耗和性能速度的平衡。

    Method and apparatus for DRAM spatial coalescing within a single channel
    10.
    发明授权
    Method and apparatus for DRAM spatial coalescing within a single channel 有权
    在单个通道内进行DRAM空间聚结的方法和装置

    公开(公告)号：US09396109B2

    公开(公告)日：2016-07-19

    申请号：US14142573

    申请日：2013-12-27

    Applicant: QUALCOMM Incorporated

    Inventor： Dexter Tamio Chun ,  Haw-Jing Lo ,  Michael Drop

    IPC: G06F12/06 ,  G06F1/32 ,  G06F13/16

    CPC classification number: G06F12/06 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1673 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

    Abstract translation: 方面包括用于重新组织存储器中的数据存储器的计算设备，系统和方法，以激励小于用于读取或写入事务的存储器模块的所有存储器设备。 存储器件可以连接到单独的选择线，使得重新排序逻辑可以根据重新排序的存储器映射来确定存储器件激活事务。 重新排序逻辑可以重新排序存储器地址，使得由处理器为交易提供的存储器地址根据重新排序的存储器映射被转换为重新排序的存储器地址，而处理器不必改变其存储器地址方案。 重新排序的存储器映射可以提供由存储器件减少的能量消耗，或等待容忍过程的能量消耗和性能速度的平衡。

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