公开(公告)号：US20140327496A1

公开(公告)日：2014-11-06

申请号：US13887568

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

Abstract translation: 公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。 在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。 可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。 通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。

公开(公告)号：US20180316374A1

公开(公告)日：2018-11-01

申请号：US16029432

申请日：2018-07-06

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Chengjie Zuo ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu ,  Jonghae Kim ,  David Berdy

IPC: H04B1/16 ,  H01L49/02 ,  H01L23/522 ,  H01L23/00 ,  H01L27/01 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H04B1/00

CPC classification number: H04B1/1638 ,  H01F17/0013 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/64 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L27/01 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2223/6688 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H04B1/006 ,  H05K1/165 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/097 ,  H05K2201/09827

Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

公开(公告)号：US20170365570A1

公开(公告)日：2017-12-21

申请号：US15184841

申请日：2016-06-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Chengjie Zuo ,  Mario Velez ,  Changhan Yun ,  Jonghae Kim

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L21/6836 ,  H01L21/4846 ,  H01L21/78 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05647 ,  H01L2224/32265 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

Abstract: Some implementations provide a device that includes a passive component and a substrate coupled to the passive component, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate. Some implementations provide an integrated device that includes a device layer and a substrate coupled to the device layer, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate.

公开(公告)号：US20170279469A1

公开(公告)日：2017-09-28

申请号：US15080472

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Yunfei Ma ,  Chengjie Zuo ,  David Berdy ,  Daeik Kim ,  Changhan Yun ,  Je-Hsiung Lan ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Robert Mikulka ,  Jonghae Kim

IPC: H04B1/00 ,  H04B1/40 ,  H04L5/14 ,  H04B1/04 ,  H04B1/3827

CPC classification number: H04B1/0057 ,  H03H7/09 ,  H03H7/463 ,  H04B1/04 ,  H04B1/3827 ,  H04B1/40 ,  H04B2001/0416 ,  H04L5/14

Abstract: An RF diplexer is provided with an integrated diplexer that shares a primary inductor included in a channel within the RF diplexer.

公开(公告)号：US09401689B2

公开(公告)日：2016-07-26

申请号：US13887568

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

公开(公告)号：US20160204758A1

公开(公告)日：2016-07-14

申请号：US15079789

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H7/01 ,  H03H3/00

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

Abstract translation: 公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。 在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。 可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。 通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。

公开(公告)号：US09355967B2

公开(公告)日：2016-05-31

申请号：US13946135

申请日：2013-07-19

Applicant: QUALCOMM Incorporated

Inventor： Daeik D. Kim ,  Je-Hsiung Lan ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Changhan Yun

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/02 ,  G06F17/50

CPC classification number: H01L23/562 ,  G06F17/5081 ,  G06F2217/80 ,  H01L21/02005 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

Abstract: An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device.

Abstract translation: 一种装置包括包括至少一层的装置。 所述至少一个层包括设备间应力补偿模式，其被配置为在所述设备从另一设备分离之前减少设备间翘曲的量。

公开(公告)号：US09203373B2

公开(公告)日：2015-12-01

申请号：US13798733

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Daeik D. Kim ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00 ,  H05K1/16 ,  H01L23/64 ,  H03H1/00 ,  H01L23/15 ,  H01L23/498 ,  H03H7/01 ,  H01F17/00 ,  H01L23/48 ,  H01L23/522 ,  H05K1/02 ,  H05K1/03 ,  H01L23/66

CPC classification number: H03H7/461 ,  H01F2017/0026 ,  H01F2017/004 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L23/66 ,  H01L2924/0002 ,  H03H3/00 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0021 ,  H05K1/0233 ,  H05K1/0306 ,  H05K1/165 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/10015 ,  H05K2201/10098 ,  Y10T29/49128 ,  H01L2924/00

Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.

Abstract translation: 双工器包括具有一组通过衬底通孔的衬底。 双工器还包括在衬底的第一表面上的第一组迹线。 第一迹线耦合到贯穿衬底通孔。 双工器还包括与第一表面相对的在衬底的第二表面上的第二组迹线。 第二迹线耦合到该组通过衬底通孔的相对端。 贯通衬底通孔和迹线也作为3D电感器工作。 双工器还包括由基板支撑的电容器。

公开(公告)号：US20140374914A1

公开(公告)日：2014-12-25

申请号：US13946135

申请日：2013-07-19

Applicant: QUALCOMM Incorporated

Inventor： Daeik D. Kim ,  Je-Hsiung Lan ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Changhan Yun

IPC: H01L23/00 ,  G06F17/50 ,  H01L21/02

CPC classification number: H01L23/562 ,  G06F17/5081 ,  G06F2217/80 ,  H01L21/02005 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

Abstract: An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device.

Abstract translation: 一种装置包括包括至少一层的装置。 所述至少一个层包括设备间应力补偿模式，其被配置为在所述设备从另一设备分离之前减少设备间翘曲的量。

公开(公告)号：US20140268615A1

公开(公告)日：2014-09-18

申请号：US13830033

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Changhan Yun ,  Francesco Carobolante ,  Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Lawrence D. Smith ,  Matthew M. Nowak

IPC: H05K7/10 ,  H05K3/30 ,  H05K3/10

CPC classification number: H05K1/165 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0262 ,  H05K3/0091 ,  H05K3/10 ,  H05K3/30 ,  H05K7/1092 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49147 ,  Y10T29/49156

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Abstract translation: 两级供电网络包括电压调节器和插入器。 插入器包括具有嵌入式电感器的封装衬底。 嵌入式电感器包括一组迹线和一组在迹线的相对端处的通过衬底通孔。 插入器耦合到电压调节器。 两级供电网络还包括由封装基板支撑的半导体管芯。 两级供电网络还包括由包装基板支撑的电容器。 电容器可操作以提供与半导体管芯相关联的去耦电容和电容，以降低电压调节器的开关噪声。