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11.发明申请MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROCESSING DATA THEREOF 有权存储器存储器件，其存储器控制器及其处理数据的方法公开(公告)号：US20140047300A1
公开(公告)日：2014-02-13
申请号：US13662541
申请日：2012-10-28
Applicant: PHISON ELECTRONICS CORP.
Inventor： Li-Chun Liang , Tien-Ching Wang , Kuo-Hsin Lai
IPC: H03M13/13
CPC classification number: G06F11/1008 , G06F11/1044 , G06F11/1068 , G11C7/1006 , H03M13/1102 , H03M13/1515 , H03M13/19 , H03M13/271 , H03M13/2778 , H03M13/2906
Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.
Abstract translation: 提供了一种适用于可重写非易失性存储器模块的数据处理方法。 该方法包括接收第一数据流并对第一数据流执行纠错编码过程以产生对应于第一数据流的原始错误校验和校正（ECC）代码。 该方法还包括根据第二重排规则将原始ECC码转换成第二ECC码，并且原始ECC码与第二ECC码不同。 该方法还包括分别将第一数据流和第二ECC码写入可重写非易失性存储器模块中相同或不同的物理编程单元的数据位区和纠错码位区。
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公开(公告)号：US10409674B2
公开(公告)日：2019-09-10
申请号：US15084454
申请日：2016-03-29
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Tien-Ching Wang , Kuo-Hsin Lai
Abstract: A decoding method for a rewritable non-volatile memory module is provided. The method includes reading data from a plurality of memory cells of the rewritable non-volatile memory module according to a first voltage, wherein the data includes a user data string and an error checking and correcting code set. The method also includes decoding at least part of sub data units i the user data string according to a first decoding algorithm to obtain a plurality of decoded sub data units. The method further includes restoring a value of the corrected bit to an original bit value if a corrected bit in the decoded sub data units matches a reliability condition.
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公开(公告)号：US10067824B2
公开(公告)日：2018-09-04
申请号：US14565437
申请日：2014-12-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Shao-Wei Yen , Tien-Ching Wang , Yu-Hsiang Lin , Kuo-Hsin Lai , Li-Chun Liang
Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.
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公开(公告)号：US20170255511A1
公开(公告)日：2017-09-07
申请号：US15084454
申请日：2016-03-29
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Tien-Ching Wang , Kuo-Hsin Lai
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C11/5642 , G11C29/52 , G11C2029/0411
Abstract: A decoding method for a rewritable non-volatile memory module is provided. The method includes reading data from a plurality of memory cells of the rewritable non-volatile memory module according to a first voltage, wherein the data includes a user data string and an error checking and correcting code set. The method also includes decoding at least part of sub data units i the user data string according to a first decoding algorithm to obtain a plurality of decoded sub data units. The method further includes restoring a value of the corrected bit to an original bit value if a corrected bit in the decoded sub data units matches a reliability condition.
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15.发明申请MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE APPARATUS AND DATA ACCESSING METHOD 有权存储器控制电路单元，存储器存储器和数据访问方法公开(公告)号：US20160266791A1
公开(公告)日：2016-09-15
申请号：US14702768
申请日：2015-05-04
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Kuo-Hsin Lai , Tien-Ching Wang
IPC: G06F3/06
CPC classification number: G06F3/0688 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C16/34
Abstract: A memory control circuit unit including a plurality of data randomizer circuits and a data selection circuit is provided. When a first data stream is received from a host system, the first data stream is input into the data randomizer circuits to respectively output a plurality of second data streams. The data selection circuit selects one of the second data streams as a third data stream according to contents of the second data streams, and the third data stream is programmed into a rewritable non-volatile memory module. Accordingly, data written into the rewritable non-volatile memory module can be effectively disarranged.
Abstract translation: 提供包括多个数据随机化器电路和数据选择电路的存储器控制电路单元。 当从主机系统接收到第一数据流时，将第一数据流输入到数据随机化器电路中，以分别输出多个第二数据流。 数据选择电路根据第二数据流的内容选择第二数据流中的一个作为第三数据流，并将第三数据流编程到可重写的非易失性存储器模块中。 因此，写入可重写非易失性存储器模块的数据可以被有效地排除。
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Patent Agency Ranking
16.发明授权Memory storage device, memory controller thereof, and method for processing data thereof 有权存储器存储装置，其存储器控制器及其数据处理方法公开(公告)号：US09223648B2
公开(公告)日：2015-12-29
申请号：US13662541
申请日：2012-10-28
Applicant: PHISON ELECTRONICS CORP.
Inventor： Li-Chun Liang , Tien-Ching Wang , Kuo-Hsin Lai
CPC classification number: G06F11/1008 , G06F11/1044 , G06F11/1068 , G11C7/1006 , H03M13/1102 , H03M13/1515 , H03M13/19 , H03M13/271 , H03M13/2778 , H03M13/2906
Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.
Abstract translation: 提供了一种适用于可重写非易失性存储器模块的数据处理方法。 该方法包括接收第一数据流并对第一数据流执行纠错编码过程以产生对应于第一数据流的原始错误校验和校正（ECC）代码。 该方法还包括根据第二重排规则将原始ECC码转换成第二ECC码，并且原始ECC码与第二ECC码不同。 该方法还包括分别将第一数据流和第二ECC码写入可重写非易失性存储器模块中相同或不同的物理编程单元的数据位区和纠错码位区。
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17.发明申请DATA MANAGING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS 有权数据管理方法，存储器控制电路单元和存储器存储器公开(公告)号：US20150331742A1
公开(公告)日：2015-11-19
申请号：US14307509
申请日：2014-06-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Li-Chun Liang , Kuo-Hsin Lai , Pei-Yu Shih , Tien-Ching Wang
CPC classification number: G11C29/52 , G06F11/1012 , G06F11/106 , G06F11/1068 , G06F11/1076 , G11B20/1833 , G11C2029/0411
Abstract: A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command.
Abstract translation: 提供数据管理方法，以及存储器控制电路单元和使用该数据管理方法的存储器存储装置。 所述数据管理方法包括：根据第一读取命令从第一物理擦除单元读取第一数据流，其中所述第一数据流包括第一用户数据，第一纠错码和第一错误检测码。 该方法还包括：使用第一纠错码和错误检测码对第一用户数据进行解码，并确定第一用户数据是否被成功解码。 该方法还包括：如果第一用户数据被成功解码，则响应于第一读取命令，将通过将第一用户数据正确解码而获得的校正用户数据发送给主机系统。
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公开(公告)号：US20180374543A1
公开(公告)日：2018-12-27
申请号：US15691763
申请日：2017-08-31
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Szu-Wei Chen , Tien-Ching Wang
Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.
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19.发明授权公开(公告)号：US09639419B2
公开(公告)日：2017-05-02
申请号：US14745472
申请日：2015-06-22
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Tien-Ching Wang , Kuo-Hsin Lai
CPC classification number: G06F11/1048 , G11C29/021 , G11C29/028 , G11C29/44 , G11C2029/5004
Abstract: A read voltage level estimating method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first region of a rewritable non-volatile memory module according to a first read voltage level to obtain a first encoding unit which belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first region according to a second read voltage level to obtain a second encoding unit which belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. Accordingly, a management ability of the rewritable non-volatile memory module adopting the block code may be improved.
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公开(公告)号：US09607704B2
公开(公告)日：2017-03-28
申请号：US14682123
申请日：2015-04-09
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Tien-Ching Wang , Kuo-Hsin Lai
CPC classification number: G11C16/26 , G06F11/1048 , G11C7/1006 , G11C2029/0411
Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.
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