公开(公告)号：US20150229337A1

公开(公告)日：2015-08-13

申请号：US14194180

申请日：2014-02-28

Applicant: LSI Corporation

Inventor： AbdelHakim S. Alhussien ,  Ivana Djurdjevic ,  Yu Cai ,  Erich F. Haratsch ,  Yue Li ,  Earl T. Cohen

IPC: H03M13/35 ,  G06F11/10

CPC classification number: H03M13/35 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/2906

Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

Abstract translation: 一种装置包括控制器和自适应纠错码解码器。 控制器可以被配置为从存储器设备读取数据并写入数据。 控制器还可以被配置为以两步过程写入数据，其包括（i）在将数据写入最低有效位（LSB）页面之后，使用第一强度纠错码（LSB）检查存储在LSB页中的数据 ECC）解码过程，并且（ii）在将数据写入与LSB页面相关联的最高有效位（MSB）页面之后，使用第二强度纠错码（ECC）解码处理来检查存储在LSB和MSB页面中的数据。

公开(公告)号：US20150178152A1

公开(公告)日：2015-06-25

申请号：US14147825

申请日：2014-01-06

Applicant: LSI Corporation

Inventor： Yu Cai ,  Yunxiang Wu ,  Zhengang Chen ,  Erich Haratsch

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

CPC classification number: G06F11/1072 ,  G11C5/147 ,  G11C16/30 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/356

Abstract: Mis-programming of MSB data in flash memory is prevented by using ECC decoding logic on the flash die that error corrects the LSB values prior to the LSB values being used in conjunction with the MSB values to determine the proper reference voltage ranges. Error correcting the LSB page data prior to using it in combination with the MSB page data to determine the reference voltage ranges ensures that the reference voltage ranges will be properly determined and programmed into the flash cells.

Abstract translation: 通过在闪存芯片上使用ECC解码逻辑防止错误编程闪存中的MSB数据，该错误将LSB值与MSB值结合使用之前校正LSB值，以确定正确的参考电压范围。 在将MSB页面数据与MSB页面数据结合使用以确定参考电压范围之前，校正LSB页数据的错误确保参考电压范围将被适当地确定并编程到闪存单元中。

公开(公告)号：US20150149698A1

公开(公告)日：2015-05-28

申请号：US14094900

申请日：2013-12-03

Applicant: LSI CORPORATION

Inventor： Yu Cai ,  Yunxiang Wu ,  Zhengang Chen ,  Erich Haratsch

IPC: G11C16/34 ,  G06F3/06 ,  G11C11/56

CPC classification number: G06F3/065 ,  G11C11/5628

Abstract: Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur.

Abstract translation: 通过将已写入闪速存储器的LSB页数据的副本与使用从闪存单元读出的LSB页数据结合MSB值来复制而不是使用复制而避免MSB数据的错误编程，以确定 正确的参考电压范围被编程到相应的闪存单元中。 由于复印件没有错误，因此使用复印件与MSB值一起确定闪存单元的正确参考电压范围，确保不会发生参考电压范围的错误编程。

公开(公告)号：US08953373B1

公开(公告)日：2015-02-10

申请号：US14052252

申请日：2013-10-11

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Erich F. Haratsch ,  Yu Cai ,  Abdel-Hakim Alhussien

IPC: G11C16/04 ,  G11C16/34

CPC classification number: G11C16/3404 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

Abstract: Upon a read error, a flash memory controller adjusts a candidate reference voltage on successive read retries until either a read error no longer occurs or an optimal reference voltage is attained. Optimal reference voltages correspond to cross-points of flash memory cell voltage distributions. Cross-points can be determined by using different candidate reference voltages to read data from the memory and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the memory is used to conceptually construct a histogram. The histogram is used to estimate when a candidate reference voltage has been adjusted to a cross-point.

Abstract translation: 在读取错误时，闪速存储器控制器在连续读取重试中调整候选参考电压，直到读取错误不再发生或达到最佳参考电压。 最佳参考电压对应于闪存单元电压分布的交点。 可以通过使用不同的候选参考电压来从存储器读取数据并确定相应的决策模式来确定交点。 使用从存储器读取的数据中出现判定模式的频率来概念地构造直方图。 直方图用于估计候选参考电压何时已被调整为交叉点。

公开(公告)号：US20150363264A1

公开(公告)日：2015-12-17

申请号：US14305208

申请日：2014-06-16

Applicant: LSI Corporation

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/1072 ,  G11C7/02 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to recover data stored in the memory determined to exceed a maximum number of errors after performing a first read operation using a first read reference voltage. The controller may perform a second read operation using a second read reference voltage. The controller may identify a victim cell having a threshold voltage in a region between the first read reference voltage and the second read reference voltage. The controller may perform a third read operation on aggressor cells of the victim cell. The controller may perform a fourth read operation using the first read reference voltage with bit-fixed values on the victim cell based on a type of interference from the aggressor cells.

Abstract translation: 一种包括存储器和控制器的装置。 存储器可以被配置为处理多个读/写操作。 存储器可以包括多个存储器模块，每个存储器模块的尺寸小于存储器的总大小。 控制器可以被配置为在使用第一读取参考电压执行第一读取操作之后，恢复存储在存储器中的数据，该数据被确定为超过最大错误数。 控制器可以使用第二读取参考电压来执行第二读取操作。 控制器可以识别在第一读取参考电压和第二读取参考电压之间的区域中具有阈值电压的受害单元。 控制器可以对受害者单元的侵略者单元执行第三次读取操作。 控制器可以基于来自侵略者单元的干扰的类型，使用具有位固定值的第一读取参考电压来执行第四读取操作。

公开(公告)号：US20150293808A1

公开(公告)日：2015-10-15

申请号：US14249450

申请日：2014-04-10

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Yu Cai ,  Erich F. Haratsch

IPC: G06F11/07

CPC classification number: G11C11/5642 ,  G11C29/52 ,  G11C2029/0411

Abstract: Aspects of the disclosure pertain to methods and systems that are configured to handle excessive read noise in soft read systems. In an implementation, a method includes determining a number of unexpected patterns of a soft read of a memory cell after a soft decoding failure. The method also includes determining whether the number of unexpected patterns is greater than a threshold number of unexpected patterns. When it is determined that the number of unexpected patterns is greater than the threshold number of unexpected patterns, the method at least one of: performing at least one more soft read of the memory cell with a larger read voltage spacing than an initial read that produced the soft decoding failure; and discarding a result of one or more soft reads of the memory cell and utilizing a remainder of results of respective other soft reads of the memory.

Abstract translation: 本公开的方面涉及被配置为在软读取系统中处理过多的读取噪声的方法和系统。 在实现中，一种方法包括在软解码失败之后确定存储器单元的软读取的意外模式的数量。 该方法还包括确定意外模式的数量是否大于阈值数量的意外模式。 当确定意外图案的数量大于意外图案的阈值数量时，该方法至少以下之一：执行具有比产生的初始读取更大的读取电压间隔的存储器单元的至少一个更软读取 软解码失败; 并且丢弃存储器单元的一个或多个软读取的结果并且利用存储器的各自的其它软读取的结果的剩余部分。

公开(公告)号：US20150227418A1

公开(公告)日：2015-08-13

申请号：US14192110

申请日：2014-02-27

Applicant: LSI Corporation

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F3/0616 ,  G06F11/1016

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory.

Abstract translation: 一种包括存储器和控制器的装置。 存储器被配置为处理多个读/写操作。 存储器包括多个存储器模块。 每个存储器模块的尺寸小于存储器的总大小。 控制器被配置为（i）将来自存储器的多个块的数据分类为热读数据或非热读数据，（ii）将热读数据聚合到专用块，以及（iii）选择错误类型 校正代码以保护专用块中的热读数据。 聚合减少了对存储器耐久性的影响。

公开(公告)号：US20150199140A1

公开(公告)日：2015-07-16

申请号：US14156693

申请日：2014-01-16

Applicant: LSI Corporation

Inventor： Ning Chen ,  Yu Cai ,  Yunxiang Wu

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0688

Abstract: An apparatus having an interface to a plurality of memories and a circuit is disclosed. Each memory generally has a plurality of planes and is nonvolatile. The circuit is configured to (i) generate a plurality of codewords by encoding a plurality of data units, (ii) generate a plurality of slices by parsing the codewords, (iii) generate a plurality of pages by interleaving the slices and (iv) write the pages in parallel into respective ones of the planes.

Abstract translation: 公开了一种具有与多个存储器和电路的接口的装置。 每个存储器通常具有多个平面并且是非易失性的。 电路被配置为（i）通过对多个数据单元进行编码来生成多个码字，（ii）通过解析码字来产生多个片，（iii）通过交错片生成多个页，以及（iv） 将页面并行写入相应的平面中。

公开(公告)号：US20150113318A1

公开(公告)日：2015-04-23

申请号：US14072574

申请日：2013-11-05

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Yu Cai ,  Erich F. Haratsch

IPC: G06F11/10

CPC classification number: H03M13/1111 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1068 ,  H03M13/45 ,  H03M13/611

Abstract: Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.

Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于从固态存储器恢复数据的系统和方法。

公开(公告)号：US20150113205A1

公开(公告)日：2015-04-23

申请号：US14072530

申请日：2013-11-05

Applicant: LSI Corporation

Inventor： Yu Cai ,  Yunxiang Wu ,  Ning Chen ,  Erich F. Haratsch ,  Zhengang Chen

IPC: G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7205 ,  G11C16/08 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/3746 ,  H03M13/6505

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory.

Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于在固态存储器中回收数据的系统和方法。