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    Methods and systems for reducing decoder error floor for an electronic non-volatile computer storage apparatus
    1.
    发明授权
    Methods and systems for reducing decoder error floor for an electronic non-volatile computer storage apparatus 有权
    用于减少电子非易失性计算机存储装置的解码器错误的方法和系统

    公开(公告)号：US09513982B1

    公开(公告)日：2016-12-06

    申请号：US14273719

    申请日：2014-05-09

    Applicant: LSI Corporation

    Inventor： Yunxiang Wu ,  Ivana Djurdjevic ,  Yu Cai ,  Earl Cohen ,  Erich F. Haratsch

    IPC: G11C29/00 ,  G06F11/07

    CPC classification number: G06F11/073 ,  B29C64/153 ,  B33Y10/00 ,  B33Y30/00 ,  H05B6/101 ,  H05B6/40

    Abstract: An electronic non-volatile computer storage apparatus and methods for reducing decoder error floor for such a storage apparatus are disclosed. An analysis process it utilized to study one or more performance metrics of a decoder of the storage apparatus in order to determine various endurance points throughout the lifetime of that particular type of storage apparatus. Theses endurance points indicate when different scaling factors should be applied and/or when log-likelihood ratio should be re-measured to accommodate physical degradations over time.

    Abstract translation: 公开了一种电子非易失性计算机存储装置和用于减少这种存储装置的解码器错误的方法。 其用于研究存储装置的解码器的一个或多个性能度量的分析过程，以便确定该特定类型的存储装置的整个寿命期内的各种耐久点。 这些耐力点表明应该应用不同的比例因子和/或当应该重新测量对数似然比以适应随时间的物理退化时。

    FIXED POINT CONVERSION OF LLR VALUES BASED ON CORRELATION
    2.
    发明申请
    FIXED POINT CONVERSION OF LLR VALUES BASED ON CORRELATION 有权
    基于关联的LLR值的固定点转换

    公开(公告)号：US20150339189A1

    公开(公告)日：2015-11-26

    申请号：US14282380

    申请日：2014-05-20

    Applicant: LSI Corporation

    Inventor： Yunxiang Wu ,  Yu Cai ,  Erich F. Haratsch

    IPC: G06F11/10

    CPC classification number: H03M13/3927 ,  G06F8/65 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/3905 ,  H03M13/6325 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6588 ,  H03M13/6591

    Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value.

    Abstract translation: 一种包括存储器和控制器的装置。 存储器可以被配置为处理多个读/写操作。 存储器包括多个存储器单元，每个存储器单元的尺寸小于存储器的总大小。 控制器可以被配置为对存储器单元执行纠错码解码。 控制器可以被配置为生成各自包含实际值的多个原始对数似然比。 控制器可以被配置为将每个原始对数似然比转换成包括固定点值的转换对数似然比。 转换包括（a）缩小每个原始对数似然比的大小，以及（b）将具有缩小幅度的原始对数似然比中的每一个舍入到固定点值。

    ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING
    3.
    发明申请
    ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING 审中-公开
    在线学习和软件信息学习

    公开(公告)号：US20150294739A1

    公开(公告)日：2015-10-15

    申请号：US14249714

    申请日：2014-04-10

    Applicant: LSI Corporation

    Inventor： Yu Cai ,  Zhengang Chen ,  Yunxiang Wu ,  Erich F. Haratsch

    IPC: G11C29/50 ,  G06F11/10 ,  G06F11/07 ,  G11C29/44

    CPC classification number: G11C16/349 ,  G06F11/1012 ,  G11C11/5642 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C2029/0411

    Abstract: A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells.

    Abstract translation: 系统包括被配置为从多个存储单元读取信息的处理器。 处理器使用第一参考电压启动来自一组存储器单元的原始数据的第一次读取。 处理器还使用不同于第一参考电压的第二参考电压来启动来自存储器单元组的原始数据的第二次读取。 处理器进一步将第一次读取与第二次读取进行比较，以识别用第一次读取和第二次读取之间改变的位值读取的存储器单元。 处理器还将读取的存储器单元分配为在第一和第二读取之间变化到与第二参考电压相关联的区域的位值。 处理器进一步用改变的位值对读取的单元的数量进行计数，以产生对应于该组存储器单元的软信息的直方图。

    METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS
    7.
    发明申请
    METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS 有权
    通过提高错误率变化分配不同页面类型的用户数据和错误校正数据的方法

    公开(公告)号：US20150178149A1

    公开(公告)日：2015-06-25

    申请号：US14173108

    申请日：2014-02-05

    Applicant: LSI Corporation

    Inventor： Yu Cai ,  Ning Chen ,  Yunxiang Wu ,  Erich F. Haratsch ,  Earl T. Cohen ,  Timothy L. Canepa

    IPC: G06F11/10

    CPC classification number: G06F11/108 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1072

    Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types.

    Abstract translation: 一种装置包括存储器和控制器。 存储器包括多个存储器件。 每个存储器设备具有多个页面类型。 基于错误率变化对多个页面类型进行分类。 控制器可以被配置为将用户数据和纠错数据写入存储器。 用户数据和纠错数据被组织为超级页面。 超级页面包括多个子页面。 多个子页面被跨越多个存储器件写入，使得使用多个页面类型中的多个页面类型存储多个子页面。

    METHOD TO DYNAMICALLY UPDATE LLRs IN AN SSD DRIVE AND/OR CONTROLLER
    9.
    发明申请
    METHOD TO DYNAMICALLY UPDATE LLRs IN AN SSD DRIVE AND/OR CONTROLLER 有权
    在SSD驱动器和/或控制器中动态地更新LLR的方法

    公开(公告)号：US20150331748A1

    公开(公告)日：2015-11-19

    申请号：US14280884

    申请日：2014-05-19

    Applicant: LSI Corporation

    Inventor： Earl T. Cohen ,  Yu Cai ,  Erich F. Haratsch ,  Yunxiang Wu

    IPC: G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/1012 ,  H03M13/3927

    Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values. The controller may be configured to count a number of unsatisfied checks if the first error correction code decoding fails. The controller may be configured to generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold. The plurality of measured log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory units.

    Abstract translation: 一种包括存储器和控制器的装置。 存储器可以被配置为处理多个读/写操作。 存储器包括多个存储器单元，每个存储器单元的尺寸小于存储器的总大小。 控制器可以被配置为使用多个初始对数似然比值对存储器单元执行第一纠错码解码。 如果第一纠错码解码失败，则控制器可以被配置为对不满足的检查数进行计数。 如果不满足的检查的数量低于阈值，则控制器可以被配置为生成多个测量的对数似然比值。 多个测量对数似然比值是（a）基于使用第一纠错码解码的解码比特的计算，和（b）用于对存储器单元执行第二纠错码解码。

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