公开(公告)号：US20150229337A1

公开(公告)日：2015-08-13

申请号：US14194180

申请日：2014-02-28

Applicant: LSI Corporation

Inventor： AbdelHakim S. Alhussien ,  Ivana Djurdjevic ,  Yu Cai ,  Erich F. Haratsch ,  Yue Li ,  Earl T. Cohen

IPC: H03M13/35 ,  G06F11/10

CPC classification number: H03M13/35 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/2906

Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

Abstract translation: 一种装置包括控制器和自适应纠错码解码器。 控制器可以被配置为从存储器设备读取数据并写入数据。 控制器还可以被配置为以两步过程写入数据，其包括（i）在将数据写入最低有效位（LSB）页面之后，使用第一强度纠错码（LSB）检查存储在LSB页中的数据 ECC）解码过程，并且（ii）在将数据写入与LSB页面相关联的最高有效位（MSB）页面之后，使用第二强度纠错码（ECC）解码处理来检查存储在LSB和MSB页面中的数据。

公开(公告)号：US20150077277A1

公开(公告)日：2015-03-19

申请号：US14033854

申请日：2013-09-23

Applicant: LSI Corporation

Inventor： AbdelHakim S. Alhussien ,  Erich F. Haratsch ,  Yue Li

IPC: H03M13/29

CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M13/13 ,  H03M13/2906 ,  H03M13/2957 ,  H03M13/618 ,  H03M13/6362 ,  H04L1/0057 ,  H04Q11/0478

Abstract: A method for encoding a reduced polar code is disclosed. The method generally includes steps (A) to (C). Step (A) may generate the intermediate codeword by polar code encoding input data. Step (B) may remove one or more bits from one of (i) a first part of the intermediate codeword and (ii) a second part of the intermediate codeword. Step (C) may generate an output codeword by concatenating the first part of the intermediate codeword with the second part of the intermediate codeword after the bits are removed.

Abstract translation: 公开了一种用于编码降低的极性码的方法。 该方法通常包括步骤（A）至（C）。 步骤（A）可以通过编码输入数据的极性码产生中间码字。 步骤（B）可以从（i）中间码字的第一部分和（ii）中间码字的第二部分之一去除一个或多个比特。 步骤（C）可以通过在去除位之后连接中间码字的第一部分与中间码字的第二部分来生成输出码字。

公开(公告)号：US20150256196A1

公开(公告)日：2015-09-10

申请号：US14219279

申请日：2014-03-19

Applicant: LSI Corporation

Inventor： AbdelHakim S. Alhussien ,  Erich F. Haratsch ,  Yue Li

IPC: H03M13/09 ,  G06F11/10

CPC classification number: G06F11/1076 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/13 ,  H03M13/45 ,  H03M13/453 ,  H04L1/0054

Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.

Abstract translation: 公开了一种具有电路和与非易失性存储器的接口的装置。 电路被配置为（i）读取非易失性存储器的读通道中的多个位。 这些位用极性码编码。 该电路还被配置为（ii）基于读取信道的多个对数似然比值产生多个概率，以及（iii）基于概率对比特进行解码。