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公开(公告)号：US09368553B2
公开(公告)日：2016-06-14
申请号：US14624920
申请日：2015-02-18
发明人： Yoshiaki Asao
IPC分类号： H01L27/24 , G11C13/00 , H01L23/528 , H01L45/00
CPC分类号： H01L27/2463 , G11C13/004 , G11C13/0069 , G11C2013/005 , G11C2013/0071 , H01L23/528 , H01L27/2436 , H01L45/065 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a memory device includes a first active area, formed on the substrate, which extends in a third direction. The memory device also includes three gate electrodes, provided on the first active area, which extend in a second direction intersecting the third direction. The memory device also includes at least two or more upper-layer interconnects and at least two or more lower-layer interconnects, provided on the first active area, which extend in a first direction intersecting the second direction and the third direction. The memory device also includes first transistors of three, each of them is provided at the intersection point between the first active area and the three gate electrodes. The memory device also includes the first transistors of three are one device isolation transistor and two cell transistors.
摘要翻译： 根据一个实施例，存储器件包括形成在衬底上的第一有源区，其在第三方向上延伸。 存储器件还包括设置在第一有源区上的三个栅电极，其在与第三方向相交的第二方向上延伸。 存储器件还包括至少两个或多个上层互连和至少两个或更多个下层互连，所述至少两个或更多个下层互连设置在第一有源区上，其沿与第二方向和第三方向相交的第一方向延伸。 存储器件还包括三个第一晶体管，它们中的每一个设置在第一有源区和三个栅电极之间的交点处。 存储器件还包括三个的第一晶体管是一个器件隔离晶体管和两个单元晶体管。
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公开(公告)号：US09263666B2
公开(公告)日：2016-02-16
申请号：US14563374
申请日：2014-12-08
发明人： Takeshi Kajiyama , Yoshiaki Asao
CPC分类号： H01L43/08 , G11C11/16 , G11C11/161 , G11C11/1675 , H01L27/222 , H01L27/228 , H01L43/02 , H01L43/10
摘要： A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.
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公开(公告)号：US09263501B1
公开(公告)日：2016-02-16
申请号：US14636538
申请日：2015-03-03
发明人： Yoshiaki Asao
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： According to one embodiment, a memory device includes a first diffusion layer region on, a second diffusion layer region, a third diffusion layer region, a first gate electrode and a second gate electrode. The memory device also includes a first via contact group, a second via contact group and a variable resistance element. At least one of the plurality of first via contacts is electrically connected to the first diffusion layer region with one end and at least one of the plurality of second via contacts is electrically connected to the third diffusion layer region with one end. The variable resistance element being electrically a first interconnect layer.
摘要翻译： 根据一个实施例，存储器件包括第一扩散层区域，第二扩散层区域，第三扩散层区域，第一栅极电极和第二栅电极。 存储器件还包括第一通孔接触组，第二通孔接触组和可变电阻元件。 多个第一通孔触点中的至少一个通过一端电连接到第一扩散层区域，并且多个第二通孔触点中的至少一个与一端电连接到第三扩散层区域。 所述可变电阻元件电连接第一互连层。
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公开(公告)号：US20150137290A1
公开(公告)日：2015-05-21
申请号：US14563374
申请日：2014-12-08
发明人： Takeshi KAJIYAMA , Yoshiaki Asao
CPC分类号： H01L43/08 , G11C11/16 , G11C11/161 , G11C11/1675 , H01L27/222 , H01L27/228 , H01L43/02 , H01L43/10
摘要： A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.
摘要翻译： 一种磁性随机存取存储器，其是包括具有固定磁化方向的固定层的磁阻效应元件，其磁化方向可逆的记录层和设置在固定层与记录层之间的非磁性层的存储单元阵列 其中，布置在磁阻效应元件下方的存储单元阵列中的所有导电层由各自含有选自包括W，Mo，Ta，Ti，Zr，Nb，Cr，Hf，V，Co和 倪
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公开(公告)号：US08791535B2
公开(公告)日：2014-07-29
申请号：US13970421
申请日：2013-08-19
发明人： Yoshiaki Asao
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1675 , H01L23/528 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10 , H01L2924/0002 , H01L2924/00
摘要： A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90−atan(⅓)) degrees.
摘要翻译： 存储器包括半导体衬底。 磁性隧道结元件设置在半导体衬底之上。 每个磁性隧道结元件通过电阻状态的变化存储数据，并且数据可由电流重写。 单元晶体管设置在半导体衬底上。 当电流被施加到对应的磁性隧道结元件时，每个单元晶体管处于导通状态。 栅电极被包括在相应的单元晶体管中。 每个栅电极控制相应的单元晶体管的导通状态。 在有源区域中，提供了单元晶体管，并且有源区域以（90-atan（1/3））度的角度在与栅电极相交的延伸方向上延伸。
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公开(公告)号：US20140204653A1
公开(公告)日：2014-07-24
申请号：US14225037
申请日：2014-03-25
发明人： Toshiharu Watanabe , Yoshiaki Asao
IPC分类号： G11C13/00
CPC分类号： G11C11/165 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/404 , G11C13/0002 , G11C13/0069 , G11C2213/79 , H01L27/0207 , H01L45/1206 , H01L45/1233 , H01L45/124
摘要： A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.
摘要翻译： 半导体存储器件包括：沿第一方向延伸的多个字线; 沿与第一方向相交的第二方向延伸的第一至第三位线; 多个可变电阻元件，每个可变电阻元件具有连接到第一和第三位线中的任一个的第一端子; 多个有效区域，在与第一至第三位线交叉的同时沿与第一方向倾斜的方向延伸; 设置在有源区上的多个选择晶体管，每个具有连接到对应的一条字线的栅极，以及电流路径，其一端连接到对应的一个可变电阻元件的第二端子; 以及多个接触插头，每个接头插头将每个选择晶体管的电流通路的另一端连接到第二位线，其中每个有源区域包括共享扩散区域的两个选择晶体管，可变电阻元件包括一个 第一可变电阻元件组和第二可变电阻元件组，第一可变电阻元件组包括在第一位线下方的第二方向上排列的可变电阻元件，并且分别设置在相邻的两条字线之间，第二可变电阻元件组 包括在第三位线下方的第二方向排列的可变电阻元件，并且每个排列在相邻的两条字线之间，并且接触插头在第二位线下方的第二方向上对齐，并且分别设置在相邻的两条线之间 的字线。
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公开(公告)号：US09384829B2
公开(公告)日：2016-07-05
申请号：US13847677
申请日：2013-03-20
发明人： Hironobu Furuhashi , Iwao Kunishima , Susumu Shuto , Yoshiaki Asao , Gaku Sudo
CPC分类号： G11C13/0002 , G11C11/5678 , G11C13/0004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/065 , H01L45/1233 , H01L45/144
摘要： A memory device includes n (n being an integer of 2 or more) resistance change films being series connected to each other. Each of the resistance change films is a superlattice film in which plural pairs of a first crystal layer made of a first compound and a second crystal layer made of a second compound are alternately stacked. An average composition of the entire resistance change film or an arrangement pitch of the first crystal layers and the second crystal layers are mutually different among the n resistance change films.
摘要翻译： 存储器件包括彼此串联连接的n（n为2以上的整数）电阻变化膜。 每个电阻变化膜是超晶格膜，其中多对由第一化合物制成的第一晶体层和由第二化合物制成的第二晶体层交替堆叠。 整个电阻变化膜的平均组成或第一晶体层和第二晶体层的排列间距在n个电阻变化膜之间是相互不同的。
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