公开(公告)号：US20200241840A1

公开(公告)日：2020-07-30

申请号：US16724800

申请日：2019-12-23

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazutaka IKEGAMI ,  Shinobu FUJITA

IPC: G06F7/38 ,  G11C11/16

Abstract: According to one embodiment, an arithmetic device includes a first computational circuit including a first string, the first string having a first magnetoresistive effect element on a first conducting layer; a second computational circuit including a second strings, the second string having second magnetoresistive effect element on a second conducting layer; a third computational circuit executing computational processing using a first signal from the first computational circuit and a second signal from the second computational circuit; and a control circuit. The control circuit sets a condition on write operations with respect to at least one of the first and second magnetoresistive effect elements, based on information related to write error in at least one of the first and second magnetoresistive effect elements.

公开(公告)号：US20190295619A1

公开(公告)日：2019-09-26

申请号：US16132991

申请日：2018-09-17

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tomoaki INOKUCHI ,  Naoharu SHIMOMURA ,  Katsuhiko KOUI ,  Yuuzo KAMIGUCHI ,  Kazutaka IKEGAMI ,  Shinobu FUJITA ,  Hiroaki YODA

IPC: G11C11/16 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22

Abstract: According to one embodiment, a magnetic device includes: a first conductive layer; a first magnetoresistive effect element disposed on the first S conductive layer and including a first control terminal;and a first circuit configured to supply a first current in a first direction into the first conductive layer and apply a first control voltage to the first control terminal of the first magnetoresistive effect element, wherein in a case in which the first current is supplied to the first conductive layer, the first magnetoresistive effect element holds a value corresponding to a logical disjunction between a first value of first data in the first magnetoresistive effect element and a second value of the first control voltage corresponding to second data.

公开(公告)号：US20180301179A1

公开(公告)日：2018-10-18

申请号：US16011070

申请日：2018-06-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tomoaki INOKUCHI ,  Naoharu SHIMOMURA ,  Katsuhiko KOUI ,  Yuuzo KAMIGUCHI ,  Satoshi SHIROTORI ,  Kazutaka IKEGAMI ,  Hiroaki YODA

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1673

Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.

公开(公告)号：US20160019942A1

公开(公告)日：2016-01-21

申请号：US14867674

申请日：2015-09-28

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hiroki NOGUCHI ,  Keiko ABE ,  Kazutaka IKEGAMI ,  Shinobu FUJITA

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential.

公开(公告)号：US20200279596A1

公开(公告)日：2020-09-03

申请号：US16741246

申请日：2020-01-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tomoaki INOKUCHI ,  Katsuhiko KOUI ,  Naoharu SHIMOMURA ,  Hideyuki SUGIYAMA ,  Kazutaka IKEGAMI ,  Susumu TAKEDA ,  Satoshi TAKAYA ,  Shinobu FUJITA ,  Hiroaki YODA

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.

公开(公告)号：US20200035280A1

公开(公告)日：2020-01-30

申请号：US16299861

申请日：2019-03-12

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hideyuki SUGIYAMA ,  Kazutaka IKEGAMI ,  Naoharu SHIMOMURA

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22

Abstract: According to one embodiment, a magnetic memory apparatus includes a first stacked body and a controller. The first stacked body includes a first magnetic layer, a first counter magnetic layer, and a first intermediate layer placed between the first magnetic layer and the first counter magnetic layer. The first intermediate layer is nonmagnetic. The controller is electrically connected to the first magnetic layer and the first counter magnetic layer. The controller is configured to perform a first operation of supplying first pulse current to the first stacked body. The first pulse current includes a first constant-current period. A first electrical resistance value of the first stacked body before the supply of the first pulse current is different from a second electrical resistance value of the first stacked body after the supply of the first pulse current.

公开(公告)号：US20160247567A1

公开(公告)日：2016-08-25

申请号：US15051132

申请日：2016-02-23

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazutaka IKEGAMI ,  Hiroki NOGUCHI

IPC: G11C14/00 ,  G06F12/08 ,  G06F1/26 ,  G11C11/16 ,  G06F12/02

CPC classification number: G06F12/0875 ,  G06F1/26 ,  G06F12/0238 ,  G06F12/0868 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/452 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1697 ,  Y02D10/13

Abstract: A semiconductor storage device has a non-volatile memory, a memory controller to carry out write processing to the non-volatile memory using a write pulse, and a write pulse controller to select one of a first write mode for writing to the non-volatile memory and a second write mode for writing to the non-volatile memory with higher electric power consumption than the first write mode at higher speed than the first write mode and, when the first write mode is selected, set a pulse width of the write pulse such that the pulse width is shorter than one cycle of a clock signal used to control access to the non-volatile memory,

Abstract translation: 半导体存储装置具有非易失性存储器，使用写入脉冲对非易失性存储器进行写入处理的存储控制器，以及写入脉冲控制器，用于选择写入非易失性存储器的第一写入模式之一 存储器和第二写入模式，用于以比第一写入模式更高的速度以比第一写入模式更高的电力消耗写入非易失性存储器，并且当选择第一写入模式时，设置写入脉冲的脉冲宽度 使得脉冲宽度短于用于控制对非易失性存储器的访问的时钟信号的一个周期，

公开(公告)号：US20130322161A1

公开(公告)日：2013-12-05

申请号：US13772815

申请日：2013-02-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiroki NOGUCHI ,  Keiko ABE ,  Kazutaka IKEGAMI ,  Shinobu FUJITA

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential.

Abstract translation: 根据一个实施例，磁性随机存取存储器包括用于向第一和第二磁阻元件写入互补数据的写入电路，以及读取电路以从第一和第二磁阻元件读取互补数据。 控制电路被配置为在将第一和第二位线设置为第一电位之后将第一和第二位线改变为浮置状态，并且将浮动状态下的第一位线的电位根据 根据第二磁阻元件的电阻值将第一磁阻元件的电阻值和浮置状态下的第二位线的电位设置为第二值，将第二磁阻元件的电阻值设定为比第一电位高的第二电位 。

公开(公告)号：US20130246818A1

公开(公告)日：2013-09-19

申请号：US13772518

申请日：2013-02-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kumiko NOMURA ,  Shinobu FUJITA ,  Keiko ABE ,  Kazutaka IKEGAMI ,  Hiroki NOGUCHI

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed.

Abstract translation: 根据实施例，高速缓存设备包括高速缓冲存储器，访问控制器和功率控制器。 高速缓冲存储器分别包括与多个方式相关联的多个存储区域。 访问控制器控制对存储区域的访问。 功率控制器单独地控制提供给每个存储器区域的功率，使得提供给在预定时间内未被访问的存储区域的功率是低于使得存储区域能够操作的操作功率的待机功率。 功率控制器控制提供给存储区域的功率，使得对于很可能被访问的存储区域的待机功率具有比不太可能被访问的存储区域的待机功率值更接近操作功率的值 。