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公开(公告)号：US10896022B2
公开(公告)日：2021-01-19
申请号：US15827831
申请日：2017-11-30
IPC分类号： G06F7/24 , G06F9/30 , H03K19/177 , G06F13/16 , G06F9/54
摘要： A compare unit includes an array including a plurality of buffer pairs to receive records on one level of a plurality of levels of a hierarchical structure. A comparator is coupled to the array, and the comparator includes one input to receive one beat of one record from one buffer of a selected buffer pair of the plurality of buffer pairs coupled to the comparator. The comparator further includes another input to receive another beat of another record from another buffer of the selected buffer pair, and logic coupled to the one input and the other input to compare the one beat and the other beat to obtain a winner beat of the compare.
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公开(公告)号：US10528253B2
公开(公告)日：2020-01-07
申请号：US14533579
申请日：2014-11-05
发明人： Ekaterina M. Ambroladze , Garrett M. Drapala , Norbert Hagspiel , Sascha Junghans , Matthias Klein , Gary E. Strait
IPC分类号： G06F3/06 , G06F12/0842 , G06F13/42
摘要： A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.
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公开(公告)号：US10394733B2
公开(公告)日：2019-08-27
申请号：US15661031
申请日：2017-07-27
IPC分类号： G06F12/084 , G06F13/28 , G06F12/0811 , G06F12/0868 , G06F12/0871
摘要： A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.
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公开(公告)号：US20190163442A1
公开(公告)日：2019-05-30
申请号：US15827697
申请日：2017-11-30
IPC分类号： G06F7/24 , G06F13/16 , G06F9/30 , G06F9/54 , H03K19/177
摘要： A logic device includes a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records. The compare unit includes a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record. The logic device further includes another compare unit on another level of the plurality of levels of the hierarchical structure. The other compare unit includes another buffer pair in which one or more other buffers of the other buffer pair are adapted to store a portion of a record. A size of the one or more other buffers of the other buffer pair is insufficient to store the entire record. The one compare unit and the other compare unit are adapted to sort a plurality of records.
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公开(公告)号：US10042554B2
公开(公告)日：2018-08-07
申请号：US14946015
申请日：2015-11-19
发明人： Ekaterina M. Ambroladze , Garrett M. Drapala , Norbert Hagspiel , Sascha Junghans , Matthias Klein , Gary E. Strait
IPC分类号： G06F12/00 , G06F3/06 , G06F12/0842 , G06F13/42
摘要： A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.
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公开(公告)号：US09606891B2
公开(公告)日：2017-03-28
申请号：US14733249
申请日：2015-06-08
CPC分类号： G06F11/348 , G06F11/3027 , G06F11/349 , G06F2201/86 , H04L7/0045 , H04L7/02
摘要： An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.
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17.发明申请公开(公告)号：US20160124854A1
公开(公告)日：2016-05-05
申请号：US14533579
申请日：2014-11-05
发明人： Ekaterina M. Ambroladze , Garrett M. Drapala , Norbert Hagspiel , Sascha Junghans , Matthias Klein , Gary E. Strait
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0647 , G06F3/0659 , G06F3/0683 , G06F12/0842 , G06F13/4221 , G06F2212/271 , G06F2212/604
摘要： A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.
摘要翻译： 一种方法，计算机程序产品和系统，用于维持包括两个或多个顺序排列的存储器的数据流的正确排序，所述数据流被移动到目的地存储器设备，所述两个或多个顺序排序的存储器至少包括第一 存储和第二存储，其中第一存储被目的地存储设备拒绝。 计算机实现的方法包括将第一存储发送到目的地存储设备。 将条件请求发送到目的地存储器设备以批准将第二存储发送到目的地存储器设备，该条件请求取决于第一存储器的成功完成。 响应于接收到对应于第一商店的拒绝响应，第二商店被取消。
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18.发明申请公开(公告)号：US20150154139A1
公开(公告)日：2015-06-04
申请号：US14096574
申请日：2013-12-04
IPC分类号： G06F13/40
CPC分类号： G06F13/287 , G06F13/1642 , G06F13/1673 , G06F13/1684 , G06F13/4022
摘要： According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method may include establishing a virtual channel from a first device to a second device via a bus, the bus having a first bus capacity and a second bus capacity, the second bus capacity having greater capacity than the first bus capacity, determining whether a store command is issued for the first bus capacity, determining whether the first bus capacity is available, and allocating the second bus capacity and marking the second bus capacity as unavailable in response to the store command if the first bus capacity is unavailable.
摘要翻译： 根据本发明的实施例，公开了用于虚拟信道管理和总线复用的方法，计算机系统和装置。 该方法可以包括经由总线建立从第一设备到第二设备的虚拟通道，总线具有第一总线容量和第二总线容量，第二总线容量具有比第一总线容量更大的容量，确定存储 发出第一总线容量的命令，确定第一总线容量是否可用，并且如果第一总线容量不可用，则分配第二总线容量并且响应于存储命令将第二总线容量标记为不可用。
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公开(公告)号：US20150149716A1
公开(公告)日：2015-05-28
申请号：US14308100
申请日：2014-06-18
IPC分类号： G11C7/10 , G11C11/406
CPC分类号： G06F12/0848 , G06F12/0846 , G11C7/22 , G11C11/419 , G11C2207/2209
摘要： A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.
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公开(公告)号：US20140089607A1
公开(公告)日：2014-03-27
申请号：US14077156
申请日：2013-11-11
发明人： Norbert Hagspiel , Matthias Klein
CPC分类号： G06F9/467 , G06F13/161
摘要： According to one aspect of the present disclosure, a method and technique for input/output traffic backpressure prediction is disclosed. The method includes: performing a plurality of memory transactions; determining, for each memory transaction, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determining a median value based on the determined traffic values; determining whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicating a prediction of a backpressure condition.
摘要翻译： 根据本公开的一个方面，公开了一种用于输入/输出业务背压预测的方法和技术。 该方法包括：执行多个存储器事务; 为每个存储器事务确定对应于用于执行各个存储器事务的时间的业务值; 响应于确定相应存储器事务的业务值，基于所确定的业务量确定中值; 确定连续的中值是否递增; 并且响应于超过阈值的连续增加的中值的量，指示背压状态的预测。
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