公开(公告)号：US10566436B2

公开(公告)日：2020-02-18

申请号：US16373242

申请日：2019-04-02

申请人： International Business Machines Corporation

发明人： Julien Frougier ,  Nicolas Loubet ,  Ruilong Xie ,  Daniel Chanemougame ,  Ali Razavieh ,  Kangguo Cheng

IPC分类号： H01L29/43 ,  H01L23/525 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/3105 ,  H01L49/00 ,  H04L29/08

摘要： Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

公开(公告)号：US20200051872A1

公开(公告)日：2020-02-13

申请号：US16059319

申请日：2018-08-09

申请人： International Business Machines Corporation

发明人： Jing Guo ,  Ekmini A. De Silva ,  Nicolas Loubet ,  Indira Seshadri ,  Nelson Felix

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/108

摘要： Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

公开(公告)号：US10546945B2

公开(公告)日：2020-01-28

申请号：US16226847

申请日：2018-12-20

申请人： International Business Machines Corporation

发明人： Julien Frougier ,  Ruilong Xie ,  Steven Bentley ,  Kangguo Cheng ,  Nicolas Loubet ,  Pietro Montanini

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78

摘要： Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

公开(公告)号：US20200027791A1

公开(公告)日：2020-01-23

申请号：US16038985

申请日：2018-07-18

申请人： International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Nicolas Loubet ,  Emmanuel Augendre ,  Remi Coquand ,  Shay Reboh

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088

摘要： Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.

公开(公告)号：US10367077B1

公开(公告)日：2019-07-30

申请号：US15964573

申请日：2018-04-27

申请人： International Business Machines Corporation

发明人： Nicolas Loubet ,  Adra Carr ,  Kangguo Cheng

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L27/088

摘要： A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a plurality of unmerged fin structures each in contact with their own source/drain. The semiconductor structure further includes a contact layer formed on sidewalls and a top surface of each source/drain. The method includes at least the following operations. At least one mandrel layer is formed adjacent to at least one fin structure. The at least one fin structure and at least one source/drain is epitaxially grown in contact with the at least one fin structure and the at least one mandrel layer. The at least one mandrel layer is removed after the at least one source/drain has been epitaxially grown. At least one contact layer is formed in contact with sidewalls and a top surface of the at least one source/drain.

公开(公告)号：US10367061B1

公开(公告)日：2019-07-30

申请号：US15941525

申请日：2018-03-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Nicolas Loubet

IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/02

摘要： A technique relates to a semiconductor device. Stacks are formed each of which including two or more nanosheets separated by a high-k dielectric material. The high-k dielectric material is formed on at least a center portion of the two or more nanosheets in the stacks. A lower spacer material is on a periphery of the two or more nanosheets, and an upper spacer material is on the lower spacer material such that the upper spacer material is above a top one of the two or more nano sheets. Source and drain regions are formed on sides of the stacks.

公开(公告)号：US10283418B2

公开(公告)日：2019-05-07

申请号：US16027889

申请日：2018-07-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

发明人： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC分类号： H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161

摘要： A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.

公开(公告)号：US10170475B2

公开(公告)日：2019-01-01

申请号：US15448626

申请日：2017-03-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

发明人： Stephane Allegret-Maret ,  Kangguo Cheng ,  Bruce Doris ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417

摘要： An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

公开(公告)号：US10134759B2

公开(公告)日：2018-11-20

申请号：US14182601

申请日：2014-02-18

申请人： STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Nicolas Loubet ,  James Kuss

IPC分类号： H01L21/8238 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02

摘要： A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins. The method may further include forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer, with the first group of nanowires including the first semiconductor material and the second group of nanowires including the second semiconductor material.

公开(公告)号：US10032912B2

公开(公告)日：2018-07-24

申请号：US14588221

申请日：2014-12-31

申请人： STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Pierre Morin ,  Kangguo Cheng ,  Jody Fronheiser ,  Xiuyu Cai ,  Juntao Li ,  Shogo Mochizuki ,  Ruilong Xie ,  Hong He ,  Nicolas Loubet

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

摘要： A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.