公开(公告)号：US10211319B2

公开(公告)日：2019-02-19

申请号：US15633934

申请日：2017-06-27

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Stuart A. Sieg ,  John R. Sporre

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

公开(公告)号：US20180122947A1

公开(公告)日：2018-05-03

申请号：US15859362

申请日：2017-12-30

Applicant: International Business Machines Corporation

Inventor： Marc Adam Bergendahl ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Robert Russell Robison ,  John Ryan Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/0657 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.

公开(公告)号：US09793402B2

公开(公告)日：2017-10-17

申请号：US15344888

申请日：2016-11-07

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Gauri Karve ,  Fee Li Lie ,  Junli Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/06 ,  H01L21/3065

CPC classification number: H01L29/7848 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device comprises patterning a strained fin from a strained layer of semiconductor material arranged on a substrate, depositing a first layer of semiconductor material on the fin and exposed portions of the substrate, patterning and etching to remove a portion of the first layer of semiconductor material and a portion of the fin to expose a portion of the substrate, depositing a second layer of semiconductor material on exposed portions of the substrate and the first layer of semiconductor material, and patterning and etching to remove a portion of the second layer of semiconductor material layer and the first layer of semiconductor material to define a dummy gate stack, the dummy gate stack is operative to substantially maintain the strain in the strained fin.

公开(公告)号：US09735275B2

公开(公告)日：2017-08-15

申请号：US14974537

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Gauri Karve ,  Robert R. Robison ,  Reinaldo A. Vega

IPC: H01L21/8238 ,  H01L21/266 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/225 ,  H01L21/8234

CPC classification number: H01L29/66537 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0638 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material on the substrate, thereby forming a channel; filling a top portion of the channel with an intermediate implant forming a vertically bi-modal dopant distribution, with one doping concentration peak in the top portion of the channel and another doping concentration peak in the punch through stopper; and patterning fins into the channel and the punch though stopper to form a finFET structure.

公开(公告)号：US20170125577A1

公开(公告)日：2017-05-04

申请号：US14932112

申请日：2015-11-04

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Gauri Karve ,  Fee Li Lie ,  Junli Wang

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/308 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device comprises patterning a strained fin from a strained layer of semiconductor material arranged on a substrate, depositing a first layer of semiconductor material on the fin and exposed portions of the substrate, patterning and etching to remove a portion of the first layer of semiconductor material and a portion of the fin to expose a portion of the substrate, depositing a second layer of semiconductor material on exposed portions of the substrate and the first layer of semiconductor material, and patterning and etching to remove a portion of the second layer of semiconductor material layer and the first layer of semiconductor material to define a dummy gate stack, the dummy gate stack is operative to substantially maintain the strain in the strained fin.

公开(公告)号：US09331148B1

公开(公告)日：2016-05-03

申请号：US14962194

申请日：2015-12-08

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底上形成翅片，在鳍片和衬底上形成虚拟栅极堆叠，去除鳍片的暴露部分的一部分，在曝光的部分上形成源极/漏极区域 在所述源极/漏极区域上形成导电接触，去除所述伪栅极堆叠以暴露所述鳍片的沟道区域，在所述鳍片的沟道区域中注入离子，执行退火处理，以及形成栅极叠层 在翅片的通道区域上。

公开(公告)号：US11869937B2

公开(公告)日：2024-01-09

申请号：US17578891

申请日：2022-01-19

Applicant: International Business Machines Corporation

Inventor： Marc Adam Bergendahl ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Robert Russell Robison ,  John Ryan Sporre ,  Sean Teehan

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0657 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

公开(公告)号：US11869936B2

公开(公告)日：2024-01-09

申请号：US17402507

申请日：2021-08-14

Applicant: International Business Machines Corporation

Inventor： Marc Adam Bergendahl ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Robert Russell Robison ,  John Ryan Sporre ,  Sean Teehan

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0657 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.

公开(公告)号：US11462631B2

公开(公告)日：2022-10-04

申请号：US16848451

申请日：2020-04-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Eric Miller ,  Fee Li Lie ,  Gauri Karve ,  Marc A. Bergendahl ,  John Ryan Sporre

IPC: H01L29/66 ,  H01L29/423 ,  H02M3/155 ,  H04L9/32 ,  H01L29/06 ,  H04L9/08 ,  B82Y10/00

Abstract: Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip includes a substrate. The semiconductor chip includes multiple devices formed on the substrate. Each device includes multiple fins. A gate is formed on the multiple fins with a gate cut (CT) design that results in random distribution of complete gate cut and incomplete gate cut for each of the multiple devices based on a natural process variation in semiconductor manufacturing for each device. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

公开(公告)号：US10832945B2

公开(公告)日：2020-11-10

申请号：US16277528

申请日：2019-02-15

Applicant: International Business Machines Corporation

Inventor： Nicole Saulnier ,  Indira Seshadri ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Gauri Karve ,  Fee Li Lie ,  Isabel Cristina Chu ,  Hosadurga Shobha ,  Ekmini A. De Silva

IPC: H01L21/768 ,  H01L21/311

Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.