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    SYSTOLIC ARRAY PROCESSOR AND OPERATING METHOD OF SYSTOLIC ARRAY PROCESSOR
    11.
    发明申请
    SYSTOLIC ARRAY PROCESSOR AND OPERATING METHOD OF SYSTOLIC ARRAY PROCESSOR 有权

    公开(公告)号：US20220164308A1

    公开(公告)日：2022-05-26

    申请号：US17523615

    申请日：2021-11-10

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Chun-Gi LYUH ,  Min-Seok CHOI ,  Young-Su KWON ,  Jin Ho HAN

    IPC: G06F15/80 ,  G06F9/54

    Abstract: Disclosed is a processor according to the present disclosure, which includes processing elements, a kernel data memory that provides a kernel data set to the processing elements, a data memory that provides an input data set to the processing elements, and a controller that provides commands to the processing elements, and a first processing element among the processing elements delays a first command received from the controller and first input data received from the data memory for a delay time, and then transfers the delayed first command and the delayed first input data to a second processing element, and the controller adjusts the delay time.

    CACHE FOR ARTIFICIAL INTELLIGENCE PROCESSOR
    12.
    发明申请
    CACHE FOR ARTIFICIAL INTELLIGENCE PROCESSOR 有权

    公开(公告)号：US20210182222A1

    公开(公告)日：2021-06-17

    申请号：US17119387

    申请日：2020-12-11

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Jin Ho HAN ,  Min-Seok CHOI ,  Young-Su KWON

    IPC: G06F13/16 ,  G06F13/28 ,  G06F12/1081 ,  G06F12/02

    Abstract: Disclosed is a cache including a dataflow controller for transmitting first data to a first processor and receiving second data from the first processor, an external direct memory access (DMA) controller for receiving the first data from an external memory to transmit the first data to the dataflow controller and receiving the second data from the dataflow controller to transmit the second data to the external memory, a scratchpad memory for storing the first data or the second data transmitted between the dataflow controller and the external DMA controller, a compression/decompression device for compressing data to be transmitted from the scratchpad memory to the external memory and decompressing data transmitted from the external memory to the scratchpad memory, and a transfer state buffer for storing transfer state information associated with data transfer between the dataflow controller and the external DMA controller.

    APPARATUS AND METHOD FOR MAINTAINING CACHE COHERENCY, AND MULTIPROCESSOR APPARATUS USING THE METHOD
    13.
    发明申请
    APPARATUS AND METHOD FOR MAINTAINING CACHE COHERENCY, AND MULTIPROCESSOR APPARATUS USING THE METHOD 有权
    用于维护高速缓存的装置和方法以及使用该方法的多处理器装置

    公开(公告)号：US20140082300A1

    公开(公告)日：2014-03-20

    申请号：US14030543

    申请日：2013-09-18

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Jin Ho HAN

    IPC: G06F12/08

    CPC classification number: G06F12/0815 ,  G06F12/0831

    Abstract: Provided are an apparatus and method for maintaining cache coherency, and a multiprocessor apparatus using the method. The multiprocessor apparatus includes a main memory, a plurality of processors, a plurality of cache memories that are connected to each of the plurality of processors, a memory bus that is connected to the plurality of cache memories and the main memory, and a coherency bus that is connected to the plurality of cache memories to transmit coherency related information between caches. Accordingly, a bandwidth shortage phenomenon may be reduced in an on-chip communication structure, which occurs when using a communication structure between a memory and a cache, and communication for coherency between caches may be simplified.

    Abstract translation: 提供了一种用于维持高速缓存一致性的装置和方法，以及使用该方法的多处理器装置。 多处理器装置包括主存储器，多个处理器，连接到多个处理器中的每一个的多个高速缓存存储器，连接到多个高速缓存存储器和主存储器的存储器总线，以及一个一致性总线 其连接到多个高速缓冲存储器以在高速缓存之间传送相关性信息。 因此，在使用存储器和高速缓存之间的通信结构时发生的片上通信结构中可能会减少带宽短缺现象，并且可以简化高速缓存之间的一致性的通信。

    CACHE CONTROL DEVICE HAVING FAULT-TOLERANT FUNCTION AND METHOD OF OPERATING THE SAME
    18.
    发明申请
    CACHE CONTROL DEVICE HAVING FAULT-TOLERANT FUNCTION AND METHOD OF OPERATING THE SAME 有权
    具有容错功能的缓存控制装置及其操作方法

    公开(公告)号：US20150309862A1

    公开(公告)日：2015-10-29

    申请号：US14690843

    申请日：2015-04-20

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Jin Ho HAN ,  Young Su KWON

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1064

    Abstract: The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation.

    Abstract translation: 具有容错功能的高速缓存控制装置包括高速缓存存储器，被配置为存储关于从主存储器读取的特定地址的第一数据，并且生成并存储对应于第一数据的第一奇偶校验位， 存储关于特定地址的第二数据，并且生成并存储与第二数据相对应的第二奇偶校验位;以及故障检测器，被配置为对存储在其中的特定地址和奇偶校验位的数据执行奇偶校验操作 当从处理器接收关于特定地址的数据读取请求时，缓存存储器和影子高速缓存存储器中的至少一个，并且根据奇偶校验操作的结果将存储在非错误存储器中的数据发送到处理器 。

    MEMORY INTERFACE DEVICE
    19.
    发明申请
    MEMORY INTERFACE DEVICE 有权

    公开(公告)号：US20220301603A1

    公开(公告)日：2022-09-22

    申请号：US17565937

    申请日：2021-12-30

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Young-Deuk JEON ,  Min-Hyung CHO ,  Young-Su KWON ,  Jin Ho HAN

    IPC: G11C7/10 ,  G11C7/22 ,  G11C8/18

    Abstract: Provided is a memory interface device. A memory interface device, comprising: a DQS input buffer configured to receive input data strobe signals and output a first intermediate data strobe signal, the DQS input buffer providing a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit provides a dynamic offset using the clean data strobe signal.

    DEVICE AND METHOD FOR CALIBRATING REFERENCE VOLTAGE
    20.
    发明申请
    DEVICE AND METHOD FOR CALIBRATING REFERENCE VOLTAGE 有权

    公开(公告)号：US20210151091A1

    公开(公告)日：2021-05-20

    申请号：US16997445

    申请日：2020-08-19

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Young-deuk JEON ,  Seong Min KIM ,  Jin Kyu KIM ,  Joo Hyun LEE ,  Min-Hyung CHO ,  Jin Ho HAN

    IPC: G11C11/4076 ,  G11C11/4099 ,  G11C11/4096

    Abstract: Disclosed are a device and a method for calibrating a reference voltage. The reference voltage calibrating device includes a data signal communication unit that transmits/receives a data signal, a data strobe signal receiving unit that receives a first data strobe signal and a second data strobe signal, a voltage level of the second data strobe signal being opposite to a voltage level of the first data strobe signal, and a reference voltage generating unit that sets a reference voltage for determining a data value of the data signal, based on the first data strobe signal and the second data strobe signal, and the reference voltage generating unit adjusts the reference voltage based on the first data strobe signal and the second data strobe signal.

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