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公开(公告)号：US20240195400A1
公开(公告)日：2024-06-13
申请号：US18454507
申请日：2023-08-23
Inventor： Min-Hyung CHO , Yi-Gyeong KIM , Su-Jin PARK , Young-Deuk JEON
CPC classification number: H03K7/08 , H03K5/05 , H03K5/131 , H03K5/15066
Abstract: Disclosed herein are an apparatus and method for monitoring the duty cycle of a memory clock signal. The apparatus for monitoring a duty cycle of a memory clock signal includes a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.
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公开(公告)号：US20240163139A1
公开(公告)日：2024-05-16
申请号：US18506544
申请日：2023-11-10
Inventor： Young-deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO , Jae-Woong CHOI
CPC classification number: H04L25/03057 , G06F13/16 , H04L25/0272 , G06F2213/16
Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.
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公开(公告)号：US20190213471A1
公开(公告)日：2019-07-11
申请号：US16222867
申请日：2018-12-17
Inventor： Young-deuk JEON , Min-Hyung CHO
IPC: G06N3/063
Abstract: Provided is a neuromorphic computing device including a differential signal generator configured to generate a plurality of first differential signals and a plurality of second differential signals on a basis of bits generated according to computation of each of a plurality of pieces of input data and each of a plurality of pieces of weight data corresponding thereto, a first capacitor synapse array configured to sample the plurality of pieces of first differential signals and output a first output voltage, a second capacitor synapse array configured to sample the plurality of pieces of second differential signals and output a second output voltage, a comparator configured to compare the first output voltage with the second output voltage to output a comparison result, and a successive approximation register (SAR) logic configured to control the first capacitor synapse array and the second capacitor synapse array on a basis of the comparison result and generate intermediate data.
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公开(公告)号：US20240194241A1
公开(公告)日：2024-06-13
申请号：US18223097
申请日：2023-07-18
Inventor： Young-Deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO , Jae-Woong CHOI
IPC: G11C11/4074 , G11C11/4076
CPC classification number: G11C11/4074 , G11C11/4076
Abstract: Disclosed herein is an apparatus for adjusting a reference voltage. The apparatus may include a gate signal generation unit for generating an RDQS gate signal, a reference voltage generation unit for setting a reference voltage based on the RDQS gate signal, and a reset counter for holding a voltage at the time at which the RDQS gate signal becomes low when the RDQS gate signal is not applied to the reference voltage generation unit for a specific time period.
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公开(公告)号：US20200174751A1
公开(公告)日：2020-06-04
申请号：US16695509
申请日：2019-11-26
Inventor： Min-Hyung CHO , Young-deuk JEON , Ki Hyuk PARK , Joo Hyun LEE
Abstract: The neuromorphic arithmetic device performs a multiply-accumulate (MAC) calculation using a multiplier and an accumulator. The neuromorphic arithmetic device includes an offset accumulator configured to receive a plurality of offset data measured a plurality of times and accumulate the plurality of offset data, a bit extractor configured to obtain average offset data by extracting at least one first bit from the plurality of accumulated offset data, and a cumulative synapse array configured to accumulate a plurality of multiplication values generated by the multiplier and output a cumulative result of the plurality of multiplication values corrected according to the average offset data.
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Patent Agency Ranking
公开(公告)号：US20180138882A1
公开(公告)日：2018-05-17
申请号：US15684625
申请日：2017-08-23
Inventor： Yi-Gyeong KIM , Woo Seok YANG , Min-Hyung CHO
IPC: H03G3/30
CPC classification number: H03G3/3089 , H03G3/3005 , H03G3/3026 , H04R1/08 , H04R3/00 , H04R2410/03
Abstract: The present disclosure relates to a microphone driving device and a digital microphone including the same. A microphone driving device according to an embodiment of the inventive concept includes a voltage-to-current converter, a current-to-voltage converter, an analog-to-digital converter, a digital amplification unit, and a gain controller. The voltage-to-current converter converts an acoustic signal to an output current signal based on a gain control signal. The current-to-voltage converter converts the output current signal to an amplified voltage signal. The analog-to-digital converter converts the amplified voltage signal to a digital signal. The digital amplification unit amplifies the digital signal to an amplified digital signal based on the gain control signal. The gain controller generates a gain control signal. The microphone driving device and the digital microphone including the same according to the inventive concept may have a wide dynamic range and reduce the influence of noise.
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公开(公告)号：US20210357753A1
公开(公告)日：2021-11-18
申请号：US17317607
申请日：2021-05-11
Inventor： Jin Kyu KIM , Byung Jo KIM , Seong Min KIM , Ju-Yeob KIM , Ki Hyuk PARK , Mi Young LEE , Joo Hyun LEE , Young-deuk JEON , Min-Hyung CHO
Abstract: A method and apparatus for multi-level stepwise quantization for neural network are provided. The apparatus sets a reference level by selecting a value from among values of parameters of the neural network in a direction from a high value equal to or greater than a predetermined value to a lower value, and performs learning based on the reference level. The setting of a reference level and the performing of learning are iteratively performed until the result of the reference level learning satisfies a predetermined value and there is no variable parameter that is updated during learning among the parameters.
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公开(公告)号：US20230147293A1
公开(公告)日：2023-05-11
申请号：US17983016
申请日：2022-11-08
Inventor： Min-Hyung CHO , Young-Deuk JEON , Jin Ho HAN
IPC: G11C11/4099 , G11C5/06 , G11C5/04
CPC classification number: G11C11/4099 , G11C5/063 , G11C5/04
Abstract: A method for ZQ calibration for a data transmission driving circuit of each memory die in a memory chip package in which memory dies are stacked, includes generating a reference current through a reference resistor connected between a power terminal supplying a power voltage of the data transmission driving circuit and a ground terminal and a first transistor that is diode-connected; supplying first currents corresponding to the reference currents to a pull-up driver of each memory die; performing ZQ calibration of a pull-up driver of a corresponding memory die by comparing a first voltage formed by each first current with a reference voltage formed by the reference current in each of the plurality of memory dies; and performing ZQ calibration of a pull-down driver of the corresponding memory die based on an output impedance of the ZQ calibrated pull-up driver in each of the memory dies.
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公开(公告)号：US20210184677A1
公开(公告)日：2021-06-17
申请号：US16996389
申请日：2020-08-18
Inventor： Min-Hyung CHO , Young-deuk JEON , Seong Min KIM
IPC: H03K19/017 , H03K19/17784 , H03K19/096 , H03K19/08
Abstract: Disclosed are a memory interface circuit including an output impedance monitor, which is capable of monitoring and calibrating an output impedance of a driving circuit in real time, and a method of calibrating the output impedance. The memory interface circuit includes a control circuit that outputs a digital transmission signal, a driving circuit that outputs an output signal, based on the digital transmission signal, an output impedance monitor that outputs a pull-up monitoring signal or a pull-down monitoring signal, based on the digital transmission signal and the output signal, and an output impedance calibrator that outputs an impedance monitoring signal, based on the pull-up monitoring signal or the pull-down monitoring signal, and wherein the driving circuit calibrates output impedance based on the impedance monitoring signal.
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公开(公告)号：US20190239771A1
公开(公告)日：2019-08-08
申请号：US16248582
申请日：2019-01-15
Inventor： Min-Hyung CHO , Young-deuk JEON , Bon Tae KOO , Mun Yang PARK , Youngseok BAEK
IPC: A61B5/053 , G01N27/02 , G01N33/483 , A61B5/00
CPC classification number: A61B5/0537 , A61B5/4869 , A61B5/7278 , G01N27/028 , G01N33/4833
Abstract: The inventive concept relates to a body composition analysis system. A body composition analysis system according to an embodiment of the inventive concept includes a sinusoidal signal generator, a synchronous detector, and a bioimpedance analyzer. The sinusoidal signal generator converts a digital sinusoidal signal having a target frequency into an analog sinusoidal signal. The synchronous detector extracts a target frequency component of a bioelectrical signal generated in response to an analog sinusoidal signal based on the digital sinusoidal signal. The bioimpedance analyzer calculates the bioimpedance based on the target frequency component of the bioelectrical signal. According to the inventive concept, it is possible to improve the selectivity for extracting the target frequency component of the bioelectrical signal and to reduce the area and variations of characteristics for the implementation of the integrated circuit.
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