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公开(公告)号：US20150147854A1
公开(公告)日：2015-05-28
申请号：US14259042
申请日：2014-04-22
Inventor： Soon-Won JUNG , Jae Bon KOO , Chan Woo PARK , Bock Soon NA , Sang Chul LIM , Sang Seok LEE , Kyoung Ik CHO , Hye Yong CHU
IPC: H01L21/311 , H01L29/66
CPC classification number: H01L21/311 , G09F9/301 , H01L29/66477 , H01L51/0023 , H01L51/0055 , H01L51/0525 , H01L51/102 , H05K1/0283 , H05K1/0333 , H05K1/16 , H05K3/0017 , H05K3/007 , H05K2201/0133 , H05K2201/0162 , H05K2201/09036 , H05K2201/09045 , H05K2201/10166 , H05K2201/2009 , H05K2203/308
Abstract: Provided is a method of fabricating an electronic circuit. The method includes preparing a substrate, forming a polymer film on the substrate, patterning the polymer film to form a polymer pattern, and forming an electronic device on the polymer pattern.
Abstract translation: 提供一种制造电子电路的方法。 该方法包括制备基底，在基底上形成聚合物膜，图案化聚合物膜以形成聚合物图案，并在聚合物图案上形成电子器件。
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公开(公告)号：US20140299362A1
公开(公告)日：2014-10-09
申请号：US14244087
申请日：2014-04-03
Inventor： Chan Woo PARK , Jae Bon KOO , Soon-Won JUNG , Sang Chul LIM , Ji-Young OH , Bock Soon NA , Sang Seok LEE , Hye Yong CHU
CPC classification number: H05K1/0283 , H01L2224/04105 , H01L2224/96 , H01L2924/1815 , H05K1/189 , H05K3/284 , H05K2201/0162 , H05K2201/2009 , Y10T29/4913
Abstract: Provided are a stretchable electric circuit and a manufacturing method thereof The method for manufacturing the stretchable electric circuit includes forming a mold substrate, forming a stretchable substrate having a first flat surface and a first corrugated surface outside the first flat surface on the mold substrate, removing the mold substrate, forming a corrugated wire on the first corrugated surface, and forming an electric device connected to the corrugated wire on the first flat surface.
Abstract translation: 本发明提供一种伸缩性电路及其制造方法本发明的拉伸电路的制造方法包括：形成模具基板，在模具基板的第一平面的外侧形成具有第一平坦面和第一波纹状表面的伸缩性基板， 所述模具基板在所述第一波纹状表面上形成波纹状线，以及在所述第一平坦表面上形成连接到所述波纹状电线的电气装置。
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公开(公告)号：US20140014915A1
公开(公告)日：2014-01-16
申请号：US13763383
申请日：2013-02-08
Inventor： Jae Bon KOO , Hojun RYU , Chi-Sun HWANG , Jeong Ik LEE , Hye Yong CHU
CPC classification number: H01L51/5203 , G02F2201/44 , H01L27/3232 , H01L51/56
Abstract: Disclosed are dual mode display devices and methods of manufacturing the same. The dual mode display device may include a first substrate, a first electrode on the first substrate, a second substrate opposite to the first electrode and the first substrate, a second electrode between the second substrate and the first electrode, a third electrode between the first electrode and the second electrode, an optic switching layer between the first electrode and the third electrode, and an organic light-emitting layer between the second electrode and the third electrode.
Abstract translation: 公开了双模式显示装置及其制造方法。 双模显示装置可以包括第一基板，第一基板上的第一电极，与第一电极和第一基板相对的第二基板，第二基板和第一电极之间的第二电极，第一电极之间的第一电极 电极和第二电极，在第一电极和第三电极之间的光学开关层，以及在第二电极和第三电极之间的有机发光层。
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公开(公告)号：US20130314633A1
公开(公告)日：2013-11-28
申请号：US13830002
申请日：2013-03-14
Inventor： Jae Bon KOO , Hojun RYU , Chi-Sun HWANG , JEONG IK LEE , Hye Yong CHU
CPC classification number: H01L51/5203 , G02F1/13718 , G02F1/167 , G02F2201/44 , G02F2203/02 , H01L27/3232 , H01L33/08
Abstract: A dual mode display apparatus according to the inventive concept includes a lower substrate, a first lower electrode on the lower substrate, a light switching layer on the first lower electrode, a first upper electrode on the light switching layer, a passivation layer on the first upper electrode, a contact plug connected to the first upper electrode and penetrating the passivation layer, a second lower electrode on the contact plug and the passivation layer, an organic light-emitting layer on the second lower electrode, a second upper electrode on the organic light-emitting layer, and an upper substrate on the second upper electrode.
Abstract translation: 根据本发明的双模显示装置包括下基板，下基板上的第一下电极，第一下电极上的光切换层，光开关层上的第一上电极，第一下电极上的钝化层 上电极，连接到第一上电极并穿透钝化层的接触插塞，接触插塞和钝化层上的第二下电极，第二下电极上的有机发光层，有机发光层上的第二上电极 发光层和第二上电极上的上基板。
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公开(公告)号：US20130292160A1
公开(公告)日：2013-11-07
申请号：US13939801
申请日：2013-07-11
Inventor： Yong Suk YANG , In-Kyu YOU , Jae Bon KOO , Yong-Young NOH
CPC classification number: H01L21/4814 , H01L21/4867 , H01L23/49822 , H01L2924/0002 , H05K1/0277 , H05K1/0298 , H05K1/0306 , H05K1/0313 , H05K1/09 , H05K3/105 , H05K3/125 , H05K3/4069 , H05K2203/1105 , H05K2203/125 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
Abstract: Provided are a multi-layer interconnection structure and a manufacturing method thereof. The multi-layer interconnection structure includes a substrate; a first wiring on the substrate; an interlayer insulation layer on the first wiring; a second wiring on the interlayer insulation layer; and a via contact including at least one conductive filament penetrating through the interlayer insulation layer between the second wiring and the first wiring to be electrically connected to the first wiring and the second wiring.
Abstract translation: 提供一种多层互连结构及其制造方法。 多层互连结构包括基板; 在基板上的第一布线; 第一布线上的层间绝缘层; 层间绝缘层上的第二布线; 以及通孔接触，其包括穿过所述第二布线和所述第一布线之间的所述层间绝缘层的至少一个导电丝，以电连接到所述第一布线和所述第二布线。
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Patent Agency Ranking
公开(公告)号：US20180277684A1
公开(公告)日：2018-09-27
申请号：US15994097
申请日：2018-05-31
Inventor： Kyoung Ik CHO , Jae Bon KOO , Chan Woo PARK , Bock Soon NA , Sang Seok LEE , Sang Chul LIM , Soon-Won JUNG , Hye Yong CHU
IPC: H01L29/786 , H01L27/12 , H01L21/311 , H01L21/3105 , H01L29/66
CPC classification number: H01L29/78603 , H01L21/3105 , H01L21/31058 , H01L21/31144 , H01L27/1218 , H01L27/1266 , H01L29/66742
Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.
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公开(公告)号：US20150349136A1
公开(公告)日：2015-12-03
申请号：US14611142
申请日：2015-01-30
Inventor： Jae Bon KOO , Chan Woo PARK , Soon-Won JUNG , Bock Soon NA , Sang Chul LIM , Sang Seok LEE , Kyoung Ik CHO , Hye Yong CHU
IPC: H01L29/786 , H01L21/428 , H01L21/02 , H01L29/66
CPC classification number: H01L29/78603 , H01L21/428 , H01L21/7813 , H01L27/1218 , H01L27/124 , H01L27/1248 , H01L27/1266 , H01L27/1292 , H01L29/66969 , H01L29/7869
Abstract: Methods for manufacturing semiconductor devices according to embodiments of the present invention may include providing a sacrificial substrate including a wiring region and a device region, sequentially forming a sacrificial layer and a buffer layer on the sacrificial substrate, forming a thin-film transistor on the buffer layer of the device region, forming a device protection element surrounding the thin-film transistor within the device region, forming a flexible substrate on the buffer layer, and exposing a surface of the buffer layer by separating the sacrificial substrate by removing the sacrificial layer. Since typical semiconductor process technologies may be directly used, the process compatibility may be improved, and semiconductor devices having high resolution and high performance may be manufactured. Furthermore, since the thin-film transistor is protected by the device protection element, the deformation of semiconductor devices under flexibility conditions may be prevented, thereby improving the reliability of the semiconductor devices.
Abstract translation: 根据本发明的实施例的制造半导体器件的方法可以包括提供包括布线区域和器件区域的牺牲衬底，在牺牲衬底上依次形成牺牲层和缓冲层，在缓冲器上形成薄膜晶体管 在器件区域内形成围绕薄膜晶体管的器件保护元件，在缓冲层上形成柔性衬底，并通过去除牺牲层来分离牺牲衬底来暴露缓冲层的表面。 由于可以直接使用典型的半导体工艺技术，因此可以提高工艺兼容性，并且可以制造具有高分辨率和高性能的半导体器件。 此外，由于薄膜晶体管被器件保护元件保护，所以可以防止半导体器件在柔性条件下的变形，从而提高半导体器件的可靠性。
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公开(公告)号：US20150171354A1
公开(公告)日：2015-06-18
申请号：US14280578
申请日：2014-05-17
Inventor： Sang Seok LEE , Kyoung Ik CHO , Bock Soon NA , Sang Chul LIM , Chan Woo PARK , Soon-Won JUNG , Jae Bon KOO , Hye Yong CHU
CPC classification number: H01L27/3244 , H01L51/003 , H01L51/0094 , H01L51/0097 , H01L51/56 , Y02E10/549
Abstract: Provided is a method for fabricating a flexible display device. The method includes attaching a shape memory alloy film memorizing a shape thereof as a curved shape at a shape memory temperature or lower to a flexible substrate at a temperature higher than the shape memory temperature, forming a display device on the flexible substrate, and returning the shape memory alloy to the curved shape to remove the shape memory alloy film from the flexible substrate.
Abstract translation: 提供一种制造柔性显示装置的方法。 该方法包括将形状记忆合金膜在高于形状记忆温度的温度下将其形状记忆温度保持为形状记忆温度以下的形状记忆合金薄膜，形成柔性基板，在柔性基板上形成显示装置， 形状记忆合金到弯曲形状，以从柔性基底去除形状记忆合金膜。
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公开(公告)号：US20140085840A1
公开(公告)日：2014-03-27
申请号：US13772288
申请日：2013-02-20
Inventor： Chan Woo PARK , Jae Bon KOO , Sang Chul LIM , Ji-Young OH , Soon-Won JUNG
CPC classification number: H05K3/10 , H05K1/0283 , H05K1/0287 , H05K1/181 , H05K3/0014 , H05K3/284
Abstract: Provided is an electronic circuit including a substrate having a flat device region and a curved interconnection region. A conduction line may extend along an uneven portion in the interconnection region and may be curved. The uneven portion and the conductive line may have a wavy shape. An external force applied to the electronic circuit may be absorbed by the uneven portion and the conductive line. The electronic device may not be affected by the external force. Therefore, functions of the electronic circuit may be maintained. A method of fabricating an electronic circuit according to the present invention may easily adjust areas and positions of the interconnection region and the device region.
Abstract translation: 提供一种电子电路，其包括具有平坦器件区域和弯曲互连区域的衬底。 导线可以沿着互连区域中的不平坦部分延伸并且可以是弯曲的。 不平坦部分和导电线可以具有波浪形状。 施加到电子电路的外力可能被不平坦部分和导电线吸收。 电子设备可能不受外力的影响。 因此，可以保持电子电路的功能。 根据本发明的制造电子电路的方法可以容易地调整互连区域和器件区域的面积和位置。
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公开(公告)号：US20140077297A1
公开(公告)日：2014-03-20
申请号：US13772236
申请日：2013-02-20
Inventor： Jae Bon KOO , Soon-Won JUNG , Bock Soon NA , Chan Woo PARK , Sang Chul LIM , Ji-Young OH , Hye Yong CHU
IPC: H01L29/786 , H01L29/66
CPC classification number: H01L29/78603 , H01L29/41733 , H01L29/66742 , H01L29/786 , H01L29/78636 , H01L51/0036 , H01L51/0039 , H01L51/0043 , H01L51/0076 , H01L51/0097 , H01L51/0541 , H01L51/0545 , H01L51/102
Abstract: Provided is a thin film transistor. The thin film transistor according to an embodiment of the present invention may include a source electrode and a drain electrode buried in a first flexible substrate, a semiconductor layer disposed on the first flexible substrate to be positioned between the source electrode and the drain electrode, a gate insulating layer completely cover the semiconductor layer, and a gate electrode facing the semiconductor layer on the gate insulating layer.
Abstract translation: 提供一种薄膜晶体管。 根据本发明实施例的薄膜晶体管可以包括埋入第一柔性衬底中的源电极和漏电极，设置在第一柔性衬底上以定位在源电极和漏电极之间的半导体层， 栅极绝缘层完全覆盖半导体层，并且栅极电极面对栅极绝缘层上的半导体层。
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