公开(公告)号：US09355838B2

公开(公告)日：2016-05-31

申请号：US13880823

申请日：2012-11-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Zuqiang Wang ,  Won Seok Kim ,  Zhengping Xiong

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L21/02252 ,  H01L21/02172 ,  H01L21/02244 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: Embodiments of the invention provide an oxide TFT and a manufacturing method thereof. The oxide thin film transistor comprises: a substrate; a gate electrode formed on the substrate; a gate insulation layer covering the gate electrode; an oxide active layer formed on the gate insulation layer and comprising a source region, a drain region, and a channel between the source region and the drain region; an etching barrier layer entirely covering the active layer and the gate insulation layer; and a source electrode and a drain electrode formed on the etching barrier layer and respectively provided on both sides of the channel. The etching barrier layer is a metal layer. The oxide thin film transistor further comprises a channel protective layer, which is a non-conductive oxidation layer converted from the metal layer by performing an oxidation treatment on the metal layer.

Abstract translation: 本发明的实施例提供一种氧化物TFT及其制造方法。 所述氧化物薄膜晶体管包括：基板; 形成在所述基板上的栅电极; 覆盖栅电极的栅极绝缘层; 形成在所述栅极绝缘层上的氧化物有源层，包括源极区域，漏极区域和所述源极区域与所述漏极区域之间的沟道; 完全覆盖有源层和栅极绝缘层的蚀刻阻挡层; 以及形成在蚀刻阻挡层上并分别设置在沟道两侧的源电极和漏电极。 蚀刻阻挡层是金属层。 所述氧化物薄膜晶体管还包括沟道保护层，所述沟道保护层是通过对所述金属层进行氧化处理而从所述金属层转换的非导电氧化层。

公开(公告)号：US20150155390A1

公开(公告)日：2015-06-04

申请号：US14348699

申请日：2013-11-11

Applicant: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L29/78672 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02642 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L27/1277 ,  H01L27/1281 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/16 ,  H01L29/6675

Abstract: A manufacturing method of a polysilicon layer and a manufacturing method of a polysilicon thin film transistor. The manufacturing method of the polysilicon layer includes: providing a substrate; forming a barrier layer and a buffer layer on the substrate; disposing a plurality of grooves in the buffer layer by a patterning process, and forming crystal seeds on the buffer layer; forming an amorphous silicon layer on the buffer layer provided with the grooves and on the crystal seeds; transferring the amorphous silicon layer into a polysilicon layer using a thermal treatment process.

Abstract translation: 多晶硅层的制造方法以及多晶硅薄膜晶体管的制造方法。 多晶硅层的制造方法包括：提供基板; 在衬底上形成阻挡层和缓冲层; 通过图案化工艺在缓冲层中设置多个槽，并在缓冲层上形成晶种; 在设置有凹槽的缓冲层上和晶体晶种上形成非晶硅层; 使用热处理工艺将非晶硅层转移到多晶硅层中。

公开(公告)号：US10586814B2

公开(公告)日：2020-03-10

申请号：US16078319

申请日：2018-01-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang

IPC: H01L27/12

Abstract: A display panel includes: a base substrate; a peripheral circuit located on the base substrate, the peripheral circuit including a first circuit, a second circuit and a third circuit, and the first circuit, the second circuit and the third circuit respectively including a first electrode pattern, a second electrode pattern and a third electrode pattern; and a protection structure, located in at least one circuit of the first circuit, the second circuit and the third circuit and configured for preventing an electrode pattern from being disconnected.

公开(公告)号：US10128354B2

公开(公告)日：2018-11-13

申请号：US15519948

申请日：2016-01-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang ,  Yuqing Yang

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L21/02

Abstract: The present disclosure provides a thin film transistor, a method for manufacturing the same, an array substrate and a display device. The method for manufacturing a thin film transistor includes providing a substrate, forming a gate electrode, a gate insulating layer, an amorphous silicon material active layer and a cap layer on the substrate successively, wherein The cap layer is provided with a pattern on a side of the cap layer away from the amorphous silicon material active layer, and the pattern is composed of at least one groove along a length direction of the active layer and at least one groove along a width direction of the active layer, subjecting the amorphous silicon material active layer to laser annealing treatment to transform the amorphous silicon material active layer into a low temperature polycrystalline silicon material active layer, and removing the cap layer.

公开(公告)号：US20180217464A1

公开(公告)日：2018-08-02

申请号：US15567207

申请日：2017-04-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang

IPC: G02F1/1362 ,  G02F1/1368 ,  G02F1/1333 ,  H01L27/12

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F1/1368 ,  G02F2001/133357 ,  G02F2201/123 ,  H01L27/124 ,  H01L27/1248

Abstract: Pixel unit, array substrate, and display device, and their fabrication methods are provided. The disclosed pixel unit can include: a transistor, including a drain electrode: a pixel electrode, including a first bottom conductive layer in contact with a surface of the drain electrode and a metal layer; and a planarization layer, formed on the transistor and the first bottom conductive layer. The metal layer is electrically connected to the first bottom conductive layer through a via-hole in the planarization layer.

公开(公告)号：US20170250207A1

公开(公告)日：2017-08-31

申请号：US15309949

申请日：2016-04-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang ,  Chien Hung Liu

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1281 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1288 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78675

Abstract: A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation of forming a low temperature poly silicon active layer; a substrate has a first region and a second region; and the step includes: forming a buffer layer on the first region and the second region of the substrate, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region; or, forming the buffer layer on the first region of the substrate; forming an amorphous silicon layer on the buffer layer; performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer; and removing the poly silicon layer on the second region, and forming the low temperature poly silicon active layer on the first region.

公开(公告)号：US09543415B2

公开(公告)日：2017-01-10

申请号：US14362971

申请日：2013-12-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang ,  Chien Hung Liu

IPC: H01L21/00 ,  H01L31/062 ,  H01L29/66 ,  H01L27/12 ,  H01L49/02 ,  H01L45/00

CPC classification number: H01L29/66757 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/1288 ,  H01L28/88 ,  H01L45/1691

Abstract: The embodiments of the present invention provide a thin film transistor driving backplane and a manufacturing method thereof, and a display panel. The manufacturing method may comprise: manufacturing a backplane base disposed with a plurality of active device structures; disposing an electrode layer on the backplane base; and manufacturing the electrode layer into a source electrode, a drain electrode and a pixel electrode integrally disposed with the drain electrode by one patterning process. According to the embodiment of the present invention, the electrode layer is manufactured into a plurality of source electrodes, drain electrodes and pixel electrodes, integrally disposed with the drain electrode, by one time patterning process, so that the source electrode, the drain electrode and the pixel electrode are all at the same electrode layer, and the source electrode, the drain electrode and the pixel electrode whose formation needs two patterning processes in the existing method, is simplified to one time patterning process, so it reduces the thickness of the thin film transistor driving backplane, simplifies the manufacturing step, and saves the manufacturing cost.

Abstract translation: 本发明的实施例提供薄膜晶体管驱动背板及其制造方法和显示面板。 制造方法可以包括：制造设置有多个有源器件结构的背板基底; 在背板底座上设置电极层; 并且通过一个图案化工艺将电极层制造成与漏电极整体设置的源电极，漏电极和像素电极。 根据本发明的实施例，通过一次图案化工艺将电极层制造成与漏电极整体配置的多个源电极，漏电极和像素电极，使得源电极，漏电极和 像素电极全部处于相同的电极层，并且在现有方法中形成需要两个图案化处理的源电极，漏电极和像素电极被简化为一次图案化工艺，因此减小了薄的厚度 薄膜晶体管驱动背板，简化了制造步骤，节省了制造成本。

公开(公告)号：US09530799B2

公开(公告)日：2016-12-27

申请号：US14345344

申请日：2013-11-11

Applicant: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang

IPC: H01L29/04 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L27/1222 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L2029/7863

Abstract: A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.

Abstract translation: 多晶硅薄膜晶体管及其制造方法，阵列基板涉及显示技术领域，可以修复多晶硅中的边界缺陷和缺陷状态，抑制热载流子效应，使TFT的特性更加稳定。 多晶硅薄膜晶体管包括栅电极，源电极，漏电极和有源层，有源层至少包括沟道区，第一掺杂区，第二掺杂区和重掺杂区，第一掺杂区是 设置在通道区域的两侧，第二掺杂区域设置在远离通道区域的第一掺杂区域的侧面上; 重掺杂区域设置在与第一掺杂区域相对的第二掺杂区域的侧面上; 并且重掺杂区域中的离子的剂量位于第一掺杂区域和第二掺杂区域中的离子剂量。

公开(公告)号：US09478562B2

公开(公告)日：2016-10-25

申请号：US14646416

申请日：2014-09-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Zheng Liu ,  Zuqiang Wang ,  Jang Soon Im

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L27/32

CPC classification number: H01L27/1222 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2227/323

Abstract: An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided. The manufacturing method of an array substrate includes forming an active material layer (501), a gate insulating layer (204) and a metal thin film (502) on a base substrate (201), and forming a pattern including an active layer (203) and a pattern including a gate electrode (205), a source electrode (206), a drain electrode (207), a gate line (1063) and a data line (1061) by a first patterning process; forming a passivation layer (301) on the base substrate (201), and forming a source contact hole (302), a drain contact hole (303), and an bridge-structure contact hole (1062a) by a second patterning process; forming a transparent conductive thin film (1401) on the base substrate (201), and removing the transparent conductive thin film (1404) partially, so that a source contact section (401), a drain contact section (402), a pixel electrode (403), and an bridge structure (1062) are formed. With the manufacturing method, the use number of patterning processes is decreased.

Abstract translation: 提供阵列基板及其制造方法，显示装置，薄膜​​晶体管及其制造方法。 阵列基板的制造方法包括在基底基板（201）上形成活性物质层（501），栅极绝缘层（204）和金属薄膜（502），形成包括活性层（203）的图案 ）和通过第一图案化工艺包括栅电极（205），源电极（206），漏电极（207），栅线（1063）和数据线（1061）的图案; 在所述基底基板上形成钝化层，通过第二构图工艺形成源极接触孔，漏极接触孔和桥接结构接触孔; 在所述基底基板上形成透明导电薄膜，将所述透明导电薄膜部分地去除，使得源极接触部分，漏极接触部分，像素电极， （403）和桥结构（1062）。 通过制造方法，图案化处理的使用次数减少。

公开(公告)号：US20150289318A1

公开(公告)日：2015-10-08

申请号：US14368924

申请日：2013-11-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

Inventor： Zuqiang Wang

IPC: H05B3/00 ,  H01L21/67 ,  H01L21/324

CPC classification number: H05B3/0047 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/6776

Abstract: An annealing apparatus includes: a temperature-gradient preheating unit, configured for performing a gradient-preheating process for a substrate that is to be annealed by using a gradient temperature; a high temperature heating unit, configured for performing a high temperature heating process for the preheated substrate; and a shifting device, configured for transporting the substrate from the temperature-gradient preheating unit to the high temperature heating unit when and/or after the substrate is subjected to the gradient-preheating process. The annealing apparatus adopts a gradient heating method to perform a preheating treatment for the substrate, so the annealing efficiency is increased. An annealing process that uses the annealing apparatus is further provided.

Abstract translation: 退火装置包括：温度梯度预热单元，被配置为对通过使用梯度温度进行退火的基板进行梯度预热处理; 高温加热单元，被配置为对所述预热基板进行高温加热处理; 以及移动装置，其构造成在所述基板经受所述梯度预热处理时和/或之后将所述基板从所述温度梯度预热单元传送到所述高温加热单元。 退火装置采用梯度加热方法对基板进行预热处理，从而提高退火效率。 进一步提供使用退火装置的退火处理。